MAX3107ETG+ Maxim Integrated Products, MAX3107ETG+ Datasheet - Page 26

• Manufacturer Part Number: MAX3107ETG+
• Description: IC UART SPI/I2C 128 FIFO 24TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX3107ETG+

• Features: Internal Oscillators
• Number Of Channels: 4, QUART
• Fifo's: 128 Byte
• Protocol: RS232, RS485
• Voltage - Supply: 2.35 V ~ 3.6 V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• Mounting Type: Surface Mount
• Package / Case: 24-TQFN Exposed Pad
• Data Rate: 24 Mbps
• Supply Voltage (max): 3.3 V
• Supply Voltage (min): 2.35 V
• Supply Current: 0.64 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• No. Of Channels: 1
• Uart Features: 128-Word Transmit / Receive FIFO, Half-Duplex Echo Suppression, Shutdown And Autosleep Modes
• Supply Voltage Range: 2.35V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SPI/I
and Internal Oscillator
LSRIntEn—Line Status Register Interrupt Enable
The LSRIntEn allows routing of LSR interrupt bits to the ISR[0].
Bits 7 and 6: No Function
Bit 5: NoiseIntEn
Set the NoiseIntEn bit high to enable routing the RxNoise interrupt to LSR[0]. If NoiseIntEn is set low, RxNoise is not
routed to LSR[0].
Bit 4: RBreaklEn
Set the RBreakIEn bit high to enable routing the RxBreak interrupt to LSR[0]. If RBreakIEn is set low, RxBreak is not
routed to LSR[0].
Bit 3: FrameErrlEn
Set the FrameErrIEn bit high to enable routing the FrameErr interrupt to LSR[0]. If FrameErrIEn is set low, FrameErr is
not routed to LSR[0].
Bit 2: ParitylEn
Set the ParityIEn bit high to enable routing the RxParityErr interrupt to LSR[0]. If ParityIEn is set low, RxParityErr is not
routed to the LSR[0].
Bit 1: ROverrlEN
Set the ROverrIEn bit high to enable routing the RxOverrun interrupt to LSR[0]. If ROverrIEn is set low, RxOverrun is
not routed to LSR[0].
Bit 0: RTimoutlEn
Set the RTimoutIEn bit high to enabled routing the RTimeout interrupt to LSR[0]. If RTimoutIEn is set low, the RTimeout
is not routed to LSR[0].
26
ADDRESS:
MODE:
RESET
NAME
_____________________________________________________________________________________
BIT
2
C UART with 128-Word FIFOs
—
7
0
0x03
R/W
—
6
0
NoiseIntEn
5
0
RBreakIEn
4
0
FrameErrIEn
3
0
ParityIEn
2
0
ROverrIEn
1
0
RTimoutIEn
0
0