SC16IS741IPW,128 NXP Semiconductors, SC16IS741IPW,128 Datasheet - Page 23

• Manufacturer Part Number: SC16IS741IPW,128
• Description: IC UART 16TSSOP
• Manufacturer: NXP Semiconductors
• Type: IrDA or RS-232 or RS-485r

Specifications of SC16IS741IPW,128

• Number Of Channels: 1, UART
• Package / Case: 16-TSSOP (0.173", 4.40mm Width)
• Features: RS-485
• Fifo's: 64 Byte
• Protocol: RS232, RS485
• Voltage - Supply: 2.5V, 3.3V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Data Rate: 5 Mbps
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.3 V
• Supply Current: 6 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 2.5 V, 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935290736128

NXP Semiconductors
UJA1076_2
Product data sheet
mode. If the SBC is in Sleep mode when the wake-up event occurs, it will wake up and
enter Standby mode. The status of the wake-up pins can be read via the wake-up level
status bits (WLS1 and WLS2) in the WD_and_Status register
Note that bits WLS1 and WLS2 are only active when at least one of the wake up interrupts
is enabled (WIC1 ≠ 00 or WIC2 ≠ 00).
The sampling of the wake-up pins can be synchronized with the WBIAS signal by setting
bits WSE1 and WSE2 in the Int_Control register to 1 (if WSEx = 0, wake-up pins are
sampled continuously). The sampling will be performed on the rising edge of WBIAS (see
Figure
(WBC) in the Mode_Control register.
Figure 12
Fig 11. Wake-up pin sampling synchronized with WBIAS signal
Fig 12. Typical application for cyclic sampling of wake-up signals
11). The sampling time, 16 ms or 64 ms, is selected via the Wake Bias Control bit
Wake-up int
WAKEx pin
WBIAS pin
UJA1076
shows typical circuit for implementing cyclic sampling of the wake-up inputs.
WBIASI
(internal)
GND
All information provided in this document is subject to legal disclaimers.
BAT
WBIAS
WAKE1
WAKE2
Rev. 02 — 27 May 2010
enable bias
47 kΩ
47 kΩ
PDTA144E
High-speed CAN core system basis chip
disable bias
biasing of
switches
disable bias
sample of
WAKEx
wake level latched
(Table
sample of
WAKEx
4).
UJA1076
© NXP B.V. 2010. All rights reserved.
015aaa078
sample of
WAKEx
015aaa122
23 of 47
t