SC16C654BIB64,157 NXP Semiconductors, SC16C654BIB64,157 Datasheet - Page 18
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SC16C654BIB64,157
Manufacturer Part Number
SC16C654BIB64,157
Description
IC QUAD UART 64BYTE 64LQFP
Manufacturer
NXP Semiconductors
Datasheet
1.SC16C654BIBS528.pdf
(58 pages)
Specifications of SC16C654BIB64,157
Features
False-start Bit Detection
Number Of Channels
4, QUART
Fifo's
64 Byte
Voltage - Supply
2.5V, 3.3V, 5V
With Auto Flow Control
Yes
With Irda Encoder/decoder
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
With Cmos
Yes
Mounting Type
Surface Mount
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
935274936157
SC16C654BIB64
SC16C654BIB64
SC16C654BIB64
SC16C654BIB64
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SC16C654BIB64,157
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Philips Semiconductors
9397 750 14965
Product data sheet
6.4 Hardware flow control
6.5 Software flow control
Holding Register (RHR) has not been read following the loading of a character or the
receive trigger level has not been reached. (For a description of this timing, see
6.4 “Hardware flow
Table 6:
When automatic hardware flow control is enabled, the SC16C654B/654DB monitors the
CTS pin for a remote buffer overflow indication and controls the RTS pin for local buffer
overflows. Automatic hardware flow control is selected by setting EFR[6] (RTS) and
EFR[7] (CTS) to a logic 1. If CTS transitions from a logic 0 to a logic 1 indicating a flow
control request, ISR[5] will be set to a logic 1 (if enabled via IER[6,7]), and the
SC16C654B/654DB will suspend TX transmissions as soon as the stop bit of the
character in process is shifted out. Transmission is resumed after the CTS input returns to
a logic 0, indicating more data may be sent.
With the Auto RTS function enabled, an interrupt is generated when the receive FIFO
reaches the programmed trigger level. The RTS pin will not be forced to a logic 1
(RTS off), until the receive FIFO reaches the next trigger level. However, the RTS pin will
return to a logic 0 after the data buffer (FIFO) is unloaded to the next trigger level below
the programmed trigger. However, under the above described conditions, the
SC16C654B/654DB will continue to accept data until the receive FIFO is full.
Remark: Hardware flow control is not supported on channel D in the HVQFN48 package.
When software flow control is enabled, the SC16C654B/654DB compares one or two
sequential receive data characters with the programmed Xon/Xoff or Xoff1,2 character
value(s). If received character(s) match the programmed values, the SC16C654B/654DB
will halt transmission (TX) as soon as the current character(s) has completed
transmission. When a match occurs, the receive ready (if enabled via Xoff IER[5]) flags
will be set and the interrupt output pin (if receive interrupt is enabled) will be activated.
Following a suspension due to a match of the Xoff characters’ values, the
SC16C654B/654DB will monitor the receive data stream for a match to the Xon1,2
character value(s). If a match is found, the SC16C654B/654DB will resume operation and
clear the flags (ISR[4]). The SC16C654B/654DB offers a special Xon mode via MCR[5].
The initialized default setting of MCR[5] is a logic 0. In this state, Xoff and Xon will operate
as defined above. Setting MCR[5] to a logic 1 sets a special operational mode for the Xon
function. In this case, Xoff operates normally, however, transmission (Xon) will resume
with the next character received, that is, a match is declared simply by the receipt of an
incoming (RX) character.
Selected trigger level
(characters)
8
16
56
60
RX trigger levels
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
control”.)
Rev. 02 — 20 June 2005
INT pin activation
8
16
56
60
SC16C654B/654DB
Negate RTS or
send Xoff
(characters)
16
56
60
60
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Assert RTS or
send Xon
(characters)
0
8
16
56
Section
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