SC28L92A1BS,551 NXP Semiconductors, SC28L92A1BS,551 Datasheet - Page 47
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SC28L92A1BS,551
Manufacturer Part Number
SC28L92A1BS,551
Description
IC UART DUAL W/FIFO 44PQFP
Manufacturer
NXP Semiconductors
Series
IMPACTr
Datasheet
1.SC28L92A1B557.pdf
(73 pages)
Specifications of SC28L92A1BS,551
Features
False-start Bit Detection
Number Of Channels
2, DUART
Fifo's
16 Byte
Voltage - Supply
3.3V, 5V
With Auto Flow Control
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
With Cmos
Yes
Mounting Type
Surface Mount
Package / Case
48-VQFN Exposed Pad, 48-HVQFN, 48-SQFN, 48-DHVQFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
935281063551
SC28L92A1BS-S
SC28L92A1BS-S
SC28L92A1BS-S
SC28L92A1BS-S
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SC28L92A1BS,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
NXP Semiconductors
SC28L92_7
Product data sheet
7.3.12 Interrupt Mask Register (IMR)
The programming of this register selects which bits in the ISR causes an interrupt output.
If a bit in the ISR is a logic 1 and the corresponding bit in the IMR is also a logic 1 the
INTRN output will be asserted. If the corresponding bit in the IMR is a zero, the state of
the bit in the ISR has no effect on the INTRN output. Note that the IMR does not mask the
programmable interrupt outputs OP3 to OP7 or the reading of the ISR.
Table 59.
Table 60.
Bit
7
6
5
4
3
2
1
0
input port
change
7
Symbol
-
-
RxRDYB
FFULLB
TxRDYB
-
-
RxRDYA
FFULLA
TxRDYA
IMR - Interrupt mask register (address 0x5) bit allocation
IMR - Interrupt mask register (address 0x5) bit description
break B
change
6
Description
Input port change.
Channel B change in break.
RxB interrupt.
TxB interrupt.
Counter ready.
Channel A change in break.
RxA interrupt.
TxA interrupt.
Rev. 07 — 19 December 2007
0 = not enabled
1 = enabled
0 = not enabled
1 = enabled
0 = not enabled
1 = enabled
0 = not enabled
1 = enabled
0 = not enabled
1 = enabled
0 = not enabled
1 = enabled
0 = not enabled
1 = enabled
0 = not enabled
1 = enabled
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
RxRDYB
FFULLB
5
TxRDYB
4
counter
ready
3
break A
change
2
RxRDYA
FFULLA
SC28L92
© NXP B.V. 2007. All rights reserved.
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TxRDYA
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