OP482 Analog Devices, OP482 Datasheet

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OP482

Manufacturer Part Number
OP482
Description
Quad Low Power, High Speed JFET Operational Amplifier
Manufacturer
Analog Devices
Datasheet

Specifications of OP482

Vcc-vee
9V to 36V
Isy Per Amplifier
250µA
Packages
DIP,SOIC
-3db Bandwidth
4MHz
Slew Rate
9V/µs
Vos
200µV
Ib
3pA
# Opamps Per Pkg
4
Input Noise (nv/rthz)
36nV/rtHz

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0
FEATURES
High slew rate: 9 V/µs
Wide bandwidth: 4 MHz
Low supply current: 250 µA/amplifier max
Low offset voltage: 3 mV max
Low bias current: 100 pA max
Fast settling time
Common-mode range includes V+
Unity-gain stable
APPLICATIONS
Active filters
Fast amplifiers
Integrators
Supply current monitoring
GENERAL DESCRIPTION
The OP282/OP482 dual and quad operational amplifiers feature
excellent speed at exceptionally low supply currents. The slew
rate is typically 9 V/µs with a supply current under 250 µA per
amplifier. These unity-gain stable amplifiers have a typical gain
bandwidth of 4 MHz.
The JFET input stage of the OP282/OP482 ensures bias current
is typically a few picoamps and below 500 pA over the full
temperature range. Offset voltage is under 3 mV for the dual
and under 4 mV for the quad.
With a wide output swing, within 1.5 V of each supply, low
power consumption, and high slew rate, the OP282/OP482
are ideal for battery-powered systems or power restricted
applications. An input common-mode range that includes the
positive supply makes the OP282/OP482 an excellent choice for
high-side signal conditioning.
The OP282/OP482 are specified over the extended industrial
temperature range. The OP282 is available in the standard
8-lead narrow SOIC and MSOP packages. The OP482 is
available in PDIP and narrow SOIC packages.
Rev. F
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
Dual/Quad Low Power, High Speed
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
JFET Operational Amplifiers
Figure 4. 14-Lead Narrow-Body SOIC (S-Suffix) [R-14]
Figure 1. 8-Lead Narrow-Body SOIC (S-Suffix) [R-8]
OUT A
OUT B
Figure 3. 14-Lead PDIP (P-Suffix) [N-14]
–IN A
+IN A
+IN B
–IN B
OUT A
OUT A
OUT B
OUT A
+IN A
–IN A
–IN A
+IN A
+IN B
–IN B
+IN A
–IN A
V+
V–
V+
Figure 2. 8-Lead MSOP [RM-8]
V–
PIN CONNECTIONS
© 2004 Analog Devices, Inc. All rights reserved.
1
2
3
4
5
6
7
1
2
3
4
1
2
3
4
1
2
3
4
5
6
7
(Not to Scale)
– +
– +
OP-482
TOP VIEW
OP282
OP482
OP282
OP482
+ –
+ –
OP282/OP482
14
13
10
12
11
9
8
8
7
5
6
8
7
6
5
14
13
10
12
11
9
8
V+
OUT B
–IN B
+IN B
OUT D
–IN D
+IN D
V–
+IN C
–IN C
OUT C
V+
OUT B
–IN B
+IN B
OUT D
–IN D
+IN D
V–
+IN C
–IN C
OUT C
www.analog.com

Related parts for OP482

OP482 Summary of contents

Page 1

... V/µs with a supply current under 250 µA per amplifier. These unity-gain stable amplifiers have a typical gain bandwidth of 4 MHz. The JFET input stage of the OP282/OP482 ensures bias current is typically a few picoamps and below 500 pA over the full temperature range. Offset voltage is under 3 mV for the dual and under 4 mV for the quad ...

Page 2

... Updated Figure 23 and Figure 27 ................................................... 8 Updated Figure 29 ............................................................................ 9 Updated Figure 35 and Figure 36 ................................................. 10 Updated Figure 43 .......................................................................... 11 Changes to Applications Information.......................................... 12 Changes to Figure 44...................................................................... 12 Deleted OP282/OP482 Spice Macro Model Section.................... 9 Deleted Figure 4................................................................................ 9 Deleted OP282 Spice Marco Model ............................................. 10 Updated Outline Dimensions ....................................................... 14 Changes to Ordering Guide .......................................................... 14 High-Side Signal Conditioning ................................................ 12 Phase Inversion ...

Page 3

... Settling Time Gain Bandwidth Product Phase Margin NOISE PERFORMANCE Voltage Noise Voltage Noise Density Current Noise Density 1 The input bias and offset currents are characterized at T Symbol Conditions V OP282 OS OP282, −40°C ≤ T ≤ +85° OP482 OS OP482, −40°C ≤ T ≤ +85° ...

Page 4

... Differential Input Voltage Output Short-Circuit Duration Storage Temperature Range P-Suffix (N), S-Suffix (R), RM Packages Operating Temperature Range OP282G, OP282A, OP482G Junction Temperature Range P-Suffix (N), S-Suffix (R), RM Packages Lead Temperature Range (Soldering 60 sec) 1 For supply voltages less than ±18 V, the absolute maximum input voltage is equal to the supply voltage ...

Page 5

... LOAD CAPACITANCE (pF) Figure 7. OP282 Small Signal Overshoot vs. Load Capacitance 180 V = ±15V 25°C A 135 –45 –90 1M 10M V = ±15V 10kΩ 100 125 400 500 Rev Page OP282/OP482 VCL VCL VCL 0 –10 –20 –30 1k 10k 100k FREQUENCY (Hz) Figure 8. OP282 Closed-Loop Gain vs. Frequency 30 25 –SR 20 ...

Page 6

... OP282/OP482 1000 100 100 FREQUENCY (Hz) Figure 11. OP282 Voltage Noise Density vs. Frequency 1000 V = ±15V 25°C A 100 10 1 0.1 –15 –10 –5 0 COMMON-MODE VOLTAGE (V) Figure 12. OP282 Input Bias Current vs. Common-Mode Voltage 480 T = 25°C A 475 470 465 460 455 450 0 ±5 ±10 SUPPLY VOLTAGE (V) Figure 13 ...

Page 7

... Figure 20. OP282 Maximum Output Swing vs. Frequency 140 120 100 –20 –40 –60 100 1M 200 V = ±15V S 160 120 100 125 –2000 Figure 22. OP282 V Rev Page OP282/OP482 V = ±15V 25° 10kΩ VCL 1k 10k 100k FREQUENCY (Hz ±15V 25° 10k 100k 1M FREQUENCY (Hz) Figure 21. OP282 CMRR vs. Frequency V = ± ...

Page 8

... Rev Page VCL V = ±15V S NEGATIVE EDGE = 2k Ω 100mV p VCL POSITIVE EDGE 300 0 100 200 LOAD CAPACITANCE (pF) Figure 26. OP482 Small Signal Overshoot vs. Load Capacitance 100 VCL VCL VCL 0 –10 –20 1k 10k 100k 1M FREQUENCY (Hz) Figure 27. OP482 Closed-Loop Gain vs. Frequency 25 – + –75 – ...

Page 9

... TEMPERATURE (°C) Figure 29. OP482 Input Bias Current vs. Temperature 60 55 GBW –75 –50 – TEMPERATURE (°C) Figure 30. OP482 Phase Margin and Gain Bandwidth Product vs. Temperature 100 FREQUENCY (Hz) Figure 31. OP482 Voltage Noise Density vs. Frequency 1000 100 75 100 125 Figure 32. OP482 Input Bias Current vs. Common-Mode Voltage 5 ...

Page 10

... LOAD RESISTANCE (Ω) Figure 37. OP482 Maximum Output Voltage vs. Load Resistance V = ±15V 25° VCL VCL 100k 1M Figure 38. OP482 Power Supply Rejection Ratio (PSRR) vs. Frequency V = ±15V S 75 100 125 NEGATIVE SWING 10k Rev Page 100 +PSRR 80 –PSRR 100 1k 10k 100k FREQUENCY (Hz) ...

Page 11

... V = ±15V 25° 100mV CM –20 100 1k 10k FREQUENCY (Hz) Figure 41. OP482 Common-Mode Rejection Ratio (CMRR) vs. Frequency 700 600 500 400 300 200 100 0 –2000 –1600 –1200 –800 –400 0 400 V (µV) OS Figure 42. OP482 V Distribution P Package OS 320 280 240 200 160 120 100k ±15V ...

Page 12

... OP282/OP482 APPLICATIONS INFORMATION The OP282 and OP482 are dual and quad JFET op amps that are optimized for high speed at low power. This combination makes these amplifiers excellent choices for battery-powered or low power applications that require above average performance. Applications benefiting from this performance combination include telecommunications, geophysical exploration, portable medical equipment, and navigational instrumentation ...

Page 13

... Q, the cutoff frequency f , and gain of a 2-pole C state variable filter. OP482s have been used in this design because of their high bandwidths, low power, and low noise. This circuit takes only three packages to build because of the quad configuration of the op amps and DACs. ...

Page 14

... OP282/OP482 OUTLINE DIMENSIONS 5.00 (0.1968) 4.80 (0.1890 6.20 (0.2440) 4.00 (0.1574) 5.80 (0.2284) 3.80 (0.1497 1.27 (0.0500) BSC 1.75 (0.0688) 1.35 (0.0532) 0.25 (0.0098) 0.10 (0.0040) 0.51 (0.0201) COPLANARITY 0.25 (0.0098) 0.31 (0.0122) SEATING 0.10 0.17 (0.0067) PLANE COMPLIANT TO JEDEC STANDARDS MS-012AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS ...

Page 15

... PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN Figure 50. 14-Lead Plastic Dual-in-Line Package [PDIP] P-Suffix (N-14) Dimension shown in inches and (millimeters) Rev Page OP282/OP482 0.50 (0.0197) × 45° 0.25 (0.0098) 8° 0° 1.27 (0.0500) ...

Page 16

... OP482GP −40°C to +85°C OP482GS −40°C to +85°C OP482GS-REEL −40°C to +85°C OP482GS-REEL7 −40°C to +85°C 1 OP482GSZ −40°C to +85°C 1 OP482GSZ-REEL −40°C to +85°C 1 OP482GSZ-REEL7 −40°C to +85° Pb-free part. ...

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