DFA200AA80 Analog Devices, DFA200AA80 Datasheet
DFA200AA80
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DFA200AA80 Summary of contents
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... U.S. Patent Nos. 4,804,960; 4,814,767; 4,833,345; 4,250,445; 4,808,908; RE 30,586 REV. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices ...
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AD679–SPECIFICATIONS ( MIN AC SPECIFICATIONS unless otherwise noted) Parameter SIGNAL-TO-NOISE AND DISTORTION (S/N+D) RATIO –0.5 dB Input (Referred to –0 dB Input) –20 dB Input (Referred to –20 dB Input) –60 dB Input (Referred to –60 dB Input) ...
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DC SPECIFICATIONS ( MIN Parameter TEMPERATURE RANGE J, K Grades A, B Grades S, T Grades ACCURACY Resolution Integral Nonlinearity (INL) Differential Nonlinearity (DNL) 1 Unipolar Zero Error (@ + Bipolar Zero Error (@ +25 C) ...
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... For parallel read (14-bits) interface to 16-bit buses, see AD779. 2 For details grade and package offerings screened in accordance with MIL-STD- 883, refer to the Analog Devices Miliary Products Databook or current AD679/ 883B data sheet Plastic DIP Ceramic DIP J-Leaded Ceramic Chip Carrier. ...
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... Unused devices must be stored in conductive foam or shunts, and the foam should be discharged to the destination socket before devices are removed. For further information on ESD precautions, refer to Analog Devices’ ESD Prevention Manual. 28-Pin Ceramic DIP Package (D-28) 28-Lead Plastic DIP Package (N-28) REV ...
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AD679 28-Pin 44-Lead DIP JLCC Symbol Pin No. Pin No. AGND 7 11 AIN 6 10 BIPOFF DGND 12 DB7–DB0 26–19 40, 39, 37, 36, 35, 34, 33, 31 EOC 27 42 EOCEN ...
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NYQUIST FREQUENCY An implication of the Nyquist sampling theorem, the “Nyquist Frequency” converter is that input frequency which is one- half the sampling frequency of the converter. SIGNAL-TO-NOISE AND DISTORTION (S/N+D) RATIO S/N+D is the ratio of the ...
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AD679 CONVERSION CONTROL In synchronous mode (SYNC = HIGH), both Chip Select (CS) and Start Convert (SC) must be brought LOW to start a con- version. CS should be LOW t before SC is brought LOW asynchronous mode ...
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INPUT CONNECTIONS AND CALIBRATION The high ( input impedance of the AD679 eases the task of interfacing to high source impedances or multiplexer channel-to-channel mismatches 300 . The 10 V p-p full-scale input range accepts ...
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AD679 and digital ground planes are also desirable, with a single inter- connection point to minimize ground loops. Analog signals should be routed as far as possible from digital signals and should cross them at right angles. The AD679 incorporates ...
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... This read operation executes in a similar manner to the first and is completed during the next 160 ns. Figure 11. AD679 to ADSP-2101 Interface AD679 to Analog Devices ADSP-2100A Figure 12 demonstrates the AD679 interfaced to an ADSP-2100A. With a clock frequency of 12.5 MHz, and instruction execution in one 80 ns cycle, the digital signal processor will support the AD679 data memory interface with three hardware wait states ...
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AD679 Figure 13. Harmonic Distortion vs. Input Frequency (–0.5 dB Input) Figure 14. Total Harmonic Distortion vs. Input Frequency and Amplitude Figure 15. S/(N+D) vs. Input Frequency and Amplitude Figure 16. 5-Plot Averaged 2048 Point FFT at 128 kSPS, f ...