AT32UC3A3128S Atmel Corporation, AT32UC3A3128S Datasheet - Page 203
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AT32UC3A3128S
Manufacturer Part Number
AT32UC3A3128S
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3A3128.pdf
(91 pages)
5.AT32UC3A3128.pdf
(1012 pages)
Specifications of AT32UC3A3128S
Flash (kbytes)
128 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
110
Ext Interrupts
110
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
2
Uart
4
Lin
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
16
Temp. Sensor
No
Crypto Engine
AES
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
12
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128 PDF datasheet #3
- AT32UC3A3128 PDF datasheet #4
- AT32UC3A3128 PDF datasheet #5
- Current page: 203 of 1012
- Download datasheet (16Mb)
15.6.7.3
Figure 15-27. NWAIT Assertion in Write Access: Ready Mode (MODE.EXNWMODE = 3).
32072G–11/2011
In te rn a lly syn ch ro n ize d
N W A IT s ig n a l
A [A D _ M S B :2 ]
N B S 0 , N B S 1 ,
C L K _ S M C
A 0 , A 1
N W A IT
D [1 5 :0 ]
Ready mode
N C S
N W E
6
In Ready mode (MODE.EXNWMODE = 3), the SMC behaves differently. Normally, the SMC
begins the access by down counting the setup and pulse counters of the read/write controlling
signal. In the last cycle of the pulse phase, the resynchronized NWAIT signal is examined.
If asserted, the SMC suspends the access as shown in
15-28 on page
performed.
This mode must be selected when the external device uses deassertion of the NWAIT signal to
indicate its ability to complete the read or write operation.
If the NWAIT signal is deasserted before the end of the pulse, or asserted after the end of the
pulse of the controlling read/write signal, it has no impact on the access length as shown in
ure 15-28 on page
4
5
4
3
204. After deassertion, the access is completed: the hold step of the access is
204.
3
2
1
2
E X N W M O D E = 3 (R e a d y m o d e )
W R IT E M O D E = 1 (N W E _ co n tro lle d )
N W E P U L S E = 5
N C S W R P U L S E = 7
W rite cyc le
0
1
F R O Z E N S T A T E
0
1
Figure 15-27 on page 203
0
1
0
and
Figure
Fig-
203
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