AT32UC3A3128S Atmel Corporation, AT32UC3A3128S Datasheet - Page 563
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AT32UC3A3128S
Manufacturer Part Number
AT32UC3A3128S
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3A3128.pdf
(91 pages)
5.AT32UC3A3128.pdf
(1012 pages)
Specifications of AT32UC3A3128S
Flash (kbytes)
128 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
110
Ext Interrupts
110
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
2
Uart
4
Lin
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
16
Temp. Sensor
No
Crypto Engine
AES
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
12
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128 PDF datasheet #3
- AT32UC3A3128 PDF datasheet #4
- AT32UC3A3128 PDF datasheet #5
- Current page: 563 of 1012
- Download datasheet (16Mb)
25.6.3.12
25.6.3.13
32072G–11/2011
Framing Error
Transmit Break
The receiver is capable of detecting framing errors. A framing error has occurred if a stop bit
reads as zero. This can occur if the transmitter and receiver are not synchronized. A framing
error is reported by CSR.FRAME as soon as the error is detected, at the middle of the stop bit.
Figure 25-24. Framing Error Status
When TXRDY is set, the user can request the transmitter to generate a break condition on the
TXD line by writing a one to The Start Break bit (CR.STTBRK). The break is treated as a normal
0x00 character transmission, clearing TXRDY and TXEMPTY, but with zeroes for preambles,
start, parity, stop, and time guard bits. Writing a one to the Stop Break bit (CR.STBRK) will stop
the generation of new break characters, and send ones for TG duration or at least 12 bit periods,
ensuring that the receiver detects end of break, before resuming normal operation.
illustrates STTBRK and STPBRK effect on the TXD line.
Writing to STTBRK and STPBRK simultaneously can lead to unpredictable results. Writes to
THR before a pending break has started will be ignored.
Baud Rate (bit/sec)
200000
Baud Rate
14400
19200
28800
33400
56000
57600
9 600
FRAME
RXRDY
Clock
Write
RXD
CR
Start
Bit
D0
D1
D2
D3
Bit Time (µs)
D4
104
D5
69
52
35
30
18
17
5
D6
D7
Parity
Bit
Stop
Bit
RSTSTA = 1
Time-out (ms)
6 827
4 551
3 413
2 276
1 962
1 170
1 138
328
Figure 25-25
563
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