AT32UC3A3128S Atmel Corporation, AT32UC3A3128S Datasheet - Page 220
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AT32UC3A3128S
Manufacturer Part Number
AT32UC3A3128S
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3A3128.pdf
(91 pages)
5.AT32UC3A3128.pdf
(1012 pages)
Specifications of AT32UC3A3128S
Flash (kbytes)
128 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
110
Ext Interrupts
110
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
2
Uart
4
Lin
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
16
Temp. Sensor
No
Crypto Engine
AES
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
12
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128 PDF datasheet #3
- AT32UC3A3128 PDF datasheet #4
- AT32UC3A3128 PDF datasheet #5
- Current page: 220 of 1012
- Download datasheet (16Mb)
16.5
16.5.1
Figure 16-2. SDRAM Controller Connections to SDRAM Devices: 16-bit Data Bus Width
16.5.2
32072G–11/2011
Application Example
Hardware Interface
Software Interface
Controller
SDRAM
SDRAMC_A[0-12]
DQM[0-1]
SDCKE
D0-D31
SDWE
SDCK
SDCS
RAS
CAS
BA0
BA1
Table 16-1.
Figure 16-2 on page 220
bus width. It is important to note that this example is given for a direct connection of the devices
to the SDRAMC, without External Bus Interface or I/O Controller multiplexing.
The SDRAM address space is organized into banks, rows, and columns. The SDRAMC allows
mapping different memory types according to the values set in the SDRAMC Configuration Reg-
ister (CR).
The SDRAMC’s function is to make the SDRAM device access protocol transparent to the user.
Table 16-2 on page 221
ping seen by the user in correlation with the device structure. Various configurations are
illustrated.
Name
DQM[1:0]
SDRAMC_A[12:0]
D[15:0]
I/O Lines Description
DQM0
D0-D7
D0-D7
CS
CLK
CKE
WE
RAS
CAS
DQM
SDRAM
2Mx8
Description
Data Mask Enable Signals
Address Bus
Data Bus
to
A0-A9 A11
shows an example of SDRAM device connection using a 16-bit data
Table 16-4 on page 221
BA0
BA1
A10
SDRAMC_A10
BA1
BA0
illustrate the SDRAM device memory map-
D8-D15
DQM1
D0-D7
CS
CLK
CKE
WE
RAS
CAS
DQM
SDRAM
2Mx8
Type
Output
Output
Input/Output
A0-A9 A11
A10
BA0
BA1
SDRAMC_A10
BA1
BA0
Active Level
High
220
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