AT32UC3A3128S Atmel Corporation, AT32UC3A3128S Datasheet - Page 550
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AT32UC3A3128S
Manufacturer Part Number
AT32UC3A3128S
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3A3128.pdf
(91 pages)
5.AT32UC3A3128.pdf
(1012 pages)
Specifications of AT32UC3A3128S
Flash (kbytes)
128 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
110
Ext Interrupts
110
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
2
Uart
4
Lin
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
16
Temp. Sensor
No
Crypto Engine
AES
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
12
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128 PDF datasheet #3
- AT32UC3A3128 PDF datasheet #4
- AT32UC3A3128 PDF datasheet #5
- Current page: 550 of 1012
- Download datasheet (16Mb)
Table 25-3.
25.6.1.3
32072G–11/2011
Source Clock (Hz)
12 000 000
12 288 000
14 318 180
14 745 600
18 432 000
24 000 000
24 576 000
25 000 000
32 000 000
32 768 000
33 000 000
40 000 000
50 000 000
60 000 000
3 686 400
4 915 200
5 000 000
7 372 800
8 000 000
Fractional Baud Rate in Asynchronous Mode
Baud Rate Example (OVER=0)
Expected Baud
The baud rate is calculated with the following formula (OVER=0):
The baud rate error is calculated with the following formula. It is not recommended to work with
an error higher than 5%.
The baud rate generator has a limitation: the source frequency is always a multiple of the baud
rate. An approach to this problem is to integrate a high resolution fractional N clock generator,
outputting fractional multiples of the reference source clock. This fractional part is selected with
the Fractional Part field (BRGR.FP), and is activated by giving it a non-zero value. The resolu-
tion is one eighth of CD. The resulting baud rate is calculated using the following formula:
The modified architecture is presented below:
Rate (bit/s)
BaudRate
38 400
38 400
38 400
38 400
38 400
38 400
38 400
38 400
38 400
38 400
38 400
38 400
38 400
38 400
38 400
38 400
38 400
38 400
38 400
BaudRate
=
------------------------------------------------------------------- -
⎛
⎝
Error
8 2 OVER
(
Calculation Result
–
SelectedClock
=
=
(
1
12.00
13.02
19.53
20.00
23.30
24.00
30.00
39.06
40.00
40.69
52.08
53.33
53.71
65.10
81.38
97.66
6.00
8.00
8.14
CLKUSART
–
⎛
⎝
) CD
ExpectedBaudRate
-------------------------------------------------- -
⎛
⎝
ActualBaudRate
+
FP
------ -
8
⎞
⎠
)
⎞
⎠
⁄
(
CD
CD
12
13
20
20
23
24
30
39
40
40
52
53
54
65
81
98
×
6
8
8
⎞
⎠
16
)
Actual Baud Rate (bit/s)
38 400.00
38 400.00
39 062.50
38 400.00
38 461.54
37 500.00
38 400.00
38 908.10
38 400.00
38 400.00
38 461.54
38 400.00
38 109.76
38 461.54
38 641.51
38 194.44
38 461.54
38 580.25
38 265.31
0.00%
0.00%
1.70%
0.00%
0.16%
2.40%
0.00%
1.31%
0.00%
0.00%
0.16%
0.00%
0.76%
0.16%
0.63%
0.54%
0.16%
0.47%
0.35%
Error
550
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