AT32UC3A3128S Atmel Corporation, AT32UC3A3128S Datasheet - Page 351
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AT32UC3A3128S
Manufacturer Part Number
AT32UC3A3128S
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3A3128.pdf
(91 pages)
5.AT32UC3A3128.pdf
(1012 pages)
Specifications of AT32UC3A3128S
Flash (kbytes)
128 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
110
Ext Interrupts
110
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
2
Uart
4
Lin
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
16
Temp. Sensor
No
Crypto Engine
AES
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
12
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128 PDF datasheet #3
- AT32UC3A3128 PDF datasheet #4
- AT32UC3A3128 PDF datasheet #5
- Current page: 351 of 1012
- Download datasheet (16Mb)
19.12.3
Name:
Access Type:
Offset:
Reset Value:
• LOC: Address of the next LLI
Starting address in memory of next LLI if block chaining is enabled.
The user need to program this register to point to the first Linked List Item (LLI) in memory prior to enabling the channel if
block chaining is enabled.
The LLP register has two functions:
The logical result of the equation LLP.LOC != 0 is used to set up the type of DMA transfer (single or multi-block).
If LLP.LOC is set to 0x0, then transfers using linked lists are NOT enabled. This register must be programmed prior to
enabling the channel in order to set up the transfer type.
It (LLP.LOC != 0) contains the pointer to the next Linked Listed Item for block chaining using linked lists. In this case,
LOC[29:0] corresponds to A[31:2] of the next Linked Listed Item address
The LLPx register is also used to point to the address where write back of the control and source/destination status infor-
mation occurs after block completion.
• LMS: List Master Select
Identifies the High speed bus interface for the device that stores the next linked list item:
Table 19-3.
32072G–11/2011
LMS
0
1
Other
31
23
15
7
Linked List Pointer Register for Channel x
List Master Select
HSB Master
HSB master 1
HSB master 2
Reserved
30
22
14
6
LLPx
Read/Write
0x010 + [x * 0x58]
0x00000000
29
21
13
5
LOC[5:0]
28
20
12
4
LOC[29:22]
LOC[21:14]
LOC[13:6]
27
19
11
3
26
18
10
2
25
17
9
1
LMS
24
16
8
0
351
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