AT32UC3C164C Atmel Corporation, AT32UC3C164C Datasheet - Page 1058
AT32UC3C164C
Manufacturer Part Number
AT32UC3C164C
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.AT32UC3C0128C.pdf
(1313 pages)
4.AT32UC3C0128C.pdf
(108 pages)
Specifications of AT32UC3C164C
Flash (kbytes)
64 Kbytes
Pin Count
100
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
81
Ext Interrupts
100
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
7
Twi (i2c)
3
Uart
5
Can
2
Lin
5
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
4
Dac Resolution (bits)
12
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
20
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6 or 4.5 to 5.5
Operating Voltage (vcc)
3.0 to 3.6 or 4.5 to 5.5
Fpu
Yes
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
22
Input Capture Channels
12
Pwm Channels
19
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3C164C-AUR
Manufacturer:
ATMEL
Quantity:
1 240
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34.7.2
Name:
Access Type:
Offset:
Reset Value:
• UPD: Up/Down Timer Mode
• TSDIR: Timer Set Direction
• FILTEN: Input Digital Filter Enable
• IDXPHS: QEPI Detection Phase
• IDXINV: QEPI Phase
• PHSINVB: QEPB Phase
• PHSINVA: QEPA Phase
• EVTRGE: Event Trigger Enable
32117C–AVR-08/11
31
23
15
7
-
-
-
-
0: Up/Down functionality in Timer Mode is disabled
1: Up/Down functionality in Timer Mode is ensabled
0: The counters count up in Timer Mode
1: The counters count down in Timer Mode
The count direction is updated when a trigger (software or hardware) occurs
0: The input digital filter is disabled
1: The input digital filter is enabled
0: QEPI detection enabled when QEPA signal equals 0 and QEPB signal equals 0
1: QEPI detection enabled when QEPA signal equals 0 and QEPB signal equals 1
2: QEPI detection enabled when QEPA signal equals 1 and QEPB signal equals 0
3: QEPI detection enabled when QEPA signal equals 1 and QEPB signal equals 1
0: QEPI will not be inverted
1: QEPI will be inverted
0: QEPB will not be inverted
1: QEPB will be inverted
0: QEPA will not be inverted
1: QEPA will be inverted
0: The event trigger function is disabled
1: The event trigger function is enabled
Configuration Register
30
22
14
6
-
-
-
-
CF
Read/Write
0x04
0x00000000
FILTEN
29
21
13
5
-
-
-
EVTRGE
28
20
12
4
-
-
IDXPHS
RCCE
27
19
11
3
-
-
IDXINV
PCCE
26
18
10
2
-
-
PHSINVB
IDXE
UPD
25
17
9
1
-
AT32UC3C
PHSINVA
TSDIR
QDEC
24
16
8
0
-
1058
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