AT32UC3C164C Atmel Corporation, AT32UC3C164C Datasheet - Page 666
AT32UC3C164C
Manufacturer Part Number
AT32UC3C164C
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.AT32UC3C0128C.pdf
(1313 pages)
4.AT32UC3C0128C.pdf
(108 pages)
Specifications of AT32UC3C164C
Flash (kbytes)
64 Kbytes
Pin Count
100
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
81
Ext Interrupts
100
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
7
Twi (i2c)
3
Uart
5
Can
2
Lin
5
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
4
Dac Resolution (bits)
12
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
20
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6 or 4.5 to 5.5
Operating Voltage (vcc)
3.0 to 3.6 or 4.5 to 5.5
Fpu
Yes
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
22
Input Capture Channels
12
Pwm Channels
19
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3C164C-AUR
Manufacturer:
ATMEL
Quantity:
1 240
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3C0128C PDF datasheet #3
- AT32UC3C0128C PDF datasheet #4
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- Download datasheet (20Mb)
Figure 26-8. Peripheral Deselection
26.7.3.9
32117C–AVR-08/11
NPCS[0..3]
NPCS[0..3]
NPCS[0..3]
NPCS[0..3]
Write TDR
Write TDR
Write TDR
Write TDR
TDRE
TDRE
TDRE
TDRE
Mode fault detection
PCS = A
A
A
A
A
CSAAT = 0 and CSNAAT = 0
CSAAT = 0 and CSNAAT = 0
DLYBCT
DLYBCT
DLYBCT
DLYBCT
Figure 26-8 on page 666
CSRn.CSAAT and CSRn.CSNAAT bits.
The SPI is capable of detecting a mode fault when it is configured in master mode and NPCS0,
MOSI, MISO, and SPCK are configured as open drain through the I/O Controller with either
internal or external pullup resistors. If the I/O Controller does not have open-drain capability,
mode fault detection must be disabled by writing a one to the Mode Fault Detection bit in the MR
DLYBCS
DLYBCS
DLYBCS
PCS = B
PCS=A
A
PCS = A
A
B
shows different peripheral deselection cases and the effect of the
A
PCS = A
A
A
A
A
CSAAT = 0 and CSNAAT = 1
CSAAT = 1 and CSNAAT= 0 / 1
DLYBCT
DLYBCT
DLYBCT
DLYBCT
DLYBCS
DLYBCS
PCS = B
PCS = A
DLYBCS
A
A
PCS = A
DLYBCS
AT32UC3C
A
A
A
B
666
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