AT32UC3C164C Atmel Corporation, AT32UC3C164C Datasheet - Page 135
AT32UC3C164C
Manufacturer Part Number
AT32UC3C164C
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.AT32UC3C0128C.pdf
(1313 pages)
4.AT32UC3C0128C.pdf
(108 pages)
Specifications of AT32UC3C164C
Flash (kbytes)
64 Kbytes
Pin Count
100
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
81
Ext Interrupts
100
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
7
Twi (i2c)
3
Uart
5
Can
2
Lin
5
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
4
Dac Resolution (bits)
12
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
20
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6 or 4.5 to 5.5
Operating Voltage (vcc)
3.0 to 3.6 or 4.5 to 5.5
Fpu
Yes
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
22
Input Capture Channels
12
Pwm Channels
19
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3C164C-AUR
Manufacturer:
ATMEL
Quantity:
1 240
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9.4.3
9.4.4
9.4.5
9.5
9.5.1
9.5.1.1
32117C–AVR-08/11
Functional Description
Interrupt
Peripheral Events
Debug Operation
Initialization
Enabling and disabling the AST clock
The AST interrupt request lines are connected to the interrupt controller. Using the AST inter-
rupts requires the interrupt controller to be programmed first.
The AST peripheral events are connected via the Peripheral Event System. Refer to the Periph-
eral Event System chapter for details.
The AST prescaler and counter is frozen during debug operation, unless the Run In Debug bit in
the Development Control Register is set and the bit corresponding to the AST is set in the
Peripheral Debug Register (PDBG). Please refer to the On-Chip Debug chapter in the
AVR32UC Technical Reference Manual, and the OCD Module Configuration section, for details.
If the AST is configured in a way that requires it to be periodically serviced by the CPU through
interrupts or similar, improper operation or data loss may result during debugging.
Before enabling the AST, the internal AST clock CLK_AST_PRSC must be enabled, following
the procedure specified in
(CLOCK.CSSEL) selects the source for this clock. The Clock Enable bit in the Clock register
(CLOCK.CEN) enables the CLK_AST_PRSC.
When CLK_AST_PRSC is enabled, the AST can be enabled by writing a one to the Enable bit in
the Control Register (CR.EN).
The Clock Source Selection field (CLOCK.CSSEL) and the Clock Enable bit (CLOCK.CEN) can-
not be changed simultaneously. Special procedures must be followed for enabling and disabling
the CLK_AST_PRSC and for changing the source for this clock.
To enable CLK_AST_PRSC:
To disable the clock:
• Peripheral Bus clock (PB clock). This is the clock of the peripheral bus the AST is connected
• Generic clock (GCLK). One of the generic clocks is connected to the AST. This clock must be
• Write the selected value to CLOCK.CSSEL
• Wait until SR.CLKBUSY reads as zero
• Write a one to CLOCK.CEN, without changing CLOCK.CSSEL
• Wait until SR.CLKBUSY reads as zero
• Write a zero to CLOCK.CEN to disable the clock, without changing CLOCK.CSSEL
• Wait until SR.CLKBUSY reads as zero
to.
enabled before use, and remains enabled in sleep modes when the PB clock is active.
Section
9.5.1.1. The Clock Source Select field in the Clock register
AT32UC3C
135
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