AT32UC3C164C Atmel Corporation, AT32UC3C164C Datasheet - Page 905
AT32UC3C164C
Manufacturer Part Number
AT32UC3C164C
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.AT32UC3C0128C.pdf
(1313 pages)
4.AT32UC3C0128C.pdf
(108 pages)
Specifications of AT32UC3C164C
Flash (kbytes)
64 Kbytes
Pin Count
100
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
81
Ext Interrupts
100
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
7
Twi (i2c)
3
Uart
5
Can
2
Lin
5
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
4
Dac Resolution (bits)
12
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
20
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6 or 4.5 to 5.5
Operating Voltage (vcc)
3.0 to 3.6 or 4.5 to 5.5
Fpu
Yes
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
22
Input Capture Channels
12
Pwm Channels
19
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3C164C-AUR
Manufacturer:
ATMEL
Quantity:
1 240
- AT32UC3A0128 PDF datasheet
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• FRZCLK: Freeze USB Clock
• VBUSPO: VBUS Polarity
• OTGPADE: OTG Pad Enable
• HNPREQ: HNP Request
• SRPREQ: SRP Request
• SRPSEL: SRP Selection
• VBUSHWC: VBUS Hardware Control
• STOE: Suspend Time-Out Interrupt Enable
• HNPERRE: HNP Error Interrupt Enable
• ROLEEXE: Role Exchange Interrupt Enable
• BCERRE: B-Connection Error Interrupt Enable
• VBERRE: VBUS Error Interrupt Enable
32117C–AVR-08/11
1: The USBC is enabled.
This bit can be written to even if FRZCLK is one.
Writing a zero to this bit will enable USB clock inputs.
Writing a one to this bit will disable USB clock inputs. The resume detection will remain active. Unless explicitly stated, all
registers will become read-only.
0: The clock inputs are enabled.
1: The clock inputs are disabled.
This bit can be written to even if USBE is zero.
0: The USB_VBOF output signal is in its default mode (active high).
1: The USB_VBOF output signal is inverted (active low).
This bit can be written even if USBE is zero or FRZCLK is one. Disabling the USBC (by writing a zero to the USBE bit) does not
reset this bit.
0: The OTG pad is disabled.
1: The OTG pad is enabled.
This bit can be written even if USBE is zero or FRZCLK is one. Disabling the USBC (by writing a zero to the USBE bit) does not
reset this bit.
When the controller is in device mode:
Writing a zero to this bit has no effect.
Writing a one to this bit will initiate a HNP (Host Negotiation Protocol).
This bit is cleared when the controller has initiated an HNP.
When the controller is in host mode:
Writing a zero to this bit will reject a HNP.
Writing a one to this bit will accept a HNP.
Writing a zero to this bit has no effect.
Writing a one to this bit will initiate an SRP when the controller is in device mode.
This bit is cleared when the controller has initiated an SRP.
0: Data line pulsing is selected as SRP method.
1: VBUS pulsing is selected as SRP method.
0: The hardware control over the USB_VBOF output pin is enabled. The USBC resets the USB_VBOF output pin when a VBUS
problem occurs.
1: The hardware control over the USB_VBOF output pin is disabled.
0: The Suspend Time-Out Interrupt (STOI) is disabled.
1: The Suspend Time-Out Interrupt (STOI) is enabled.
0: The HNP Error Interrupt (HNPERRI) is disabled.
1: The HNP Error Interrupt (HNPERRI) is enabled.
0: The Role Exchange Interrupt (ROLEEXI) is disabled.
1: The Role Exchange Interrupt (ROLEEXI) is enabled.
0: The B-Connection Error Interrupt (BCERRI) is disabled.
1: The B-Connection Error Interrupt (BCERRI) is enabled.
0: The VBUS Error Interrupt (VBERRI) is disabled.
AT32UC3C
905
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