AT32UC3C164C Atmel Corporation, AT32UC3C164C Datasheet - Page 510
AT32UC3C164C
Manufacturer Part Number
AT32UC3C164C
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.AT32UC3C0128C.pdf
(1313 pages)
4.AT32UC3C0128C.pdf
(108 pages)
Specifications of AT32UC3C164C
Flash (kbytes)
64 Kbytes
Pin Count
100
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Max I/o Pins
81
Ext Interrupts
100
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
7
Twi (i2c)
3
Uart
5
Can
2
Lin
5
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
4
Dac Resolution (bits)
12
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
20
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6 or 4.5 to 5.5
Operating Voltage (vcc)
3.0 to 3.6 or 4.5 to 5.5
Fpu
Yes
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
22
Input Capture Channels
12
Pwm Channels
19
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3C164C-AUR
Manufacturer:
ATMEL
Quantity:
1 240
- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3C0128C PDF datasheet #3
- AT32UC3C0128C PDF datasheet #4
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- Download datasheet (20Mb)
• RTY: Retry Test
• CLK: PB Clock Divider
• EAE: External Address Match Enable
• FS: Frame Size
• UNI: Unicast Hash Enable
• MTI: Multicast Hash Enable
• NBC: No Broadcast
• JFRAME: Jumbo Frames
• CAF: Copy All Frames
• BR: Bitrate
• FD: Full Duplex
• SPD: Speed
32117C–AVR-08/11
CLK
00
01
10
11
0: Normal operation.
1: The back off between collisions is always one slot time. It helps testing the too many retries condition. Also used in the pause
frame tests to reduce the pause counters decrement time from 512 bit times, to every RX_CLK cycle.
Determines by what number system clock is divided to generate Divided PB Clock (DPC). For conformance with 802.3, DPC
must not exceed 2.5MHz (DPC is only active during MDIO read and write operations).
0: External address match is disabled.
1: External address match is enabled. Eam pin can be used to copy frames to memory.
0: Reject any frames above 1518 bytes.
1: Accept frames up to 1536 bytes.
0: Unicast hash is disabled.
1: Unicast hash is enabled. Unicast frames are received when the 6-bit hash function of the destination address points to a bit
that is set in the hash register.
0: Multicast hash is disabled.
1: Multicast hash is enabled. Multicast frames are received when the 6-bit hash function of the destination address points to a bit
that is set in the hash register.
0: Frames addressed to the broadcast address of all ones are received.
1: Frames addressed to the broadcast address of all ones are not received.
0: Jumbo frames are disabled.
1: Enable jumbo frames of up to 10240 bytes to be accepted.
0: Copy all frames is disabled.
1: All valid frames are received.
0: Data is transmitted least significant nibble first.
1: Data is serialized and transmitted least significant bit first (10Mbps). Must be written before receive and transmit enable in the
network control register. Serial interface is configured with transmit and receive data being driven out on TXD[0] and received on
RXD[0] serially. Also the CRS and RX_DV are logically ORed together so either may be used as the data valid signal.
0: Full duplex mode is disabled.
1: Full duplex mode is enabled. Transmit sub-module ignores the state of collision and carrier sense and allows receive while
transmitting. Also controls the half duplex pin.
0: 10 Mbit/s speed.
1: 100 Mbit/s speed. Bit value is reflected on the SPEED pin.
DPC
PB clock divided by 8 (PB clock up to 20 MHz)
PB clock divided by 16 (PB clock up to 40 MHz)
PB clock divided by 32 (PB clock up to 80 MHz)
PB clock divided by 64 (PB clock up to 160 MHz)
AT32UC3C
510
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