AT89LP51ED2 Atmel Corporation, AT89LP51ED2 Datasheet - Page 36

• Manufacturer Part Number: AT89LP51ED2
• Manufacturer: Atmel Corporation

Specifications of AT89LP51ED2

• Flash (kbytes): 64 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 42
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Adc Channels: 7
• Adc Resolution (bits): 10
• Adc Speed (ksps): 153.8
• Sram (kbytes): 2.25
• Eeprom (bytes): 4096
• Self Program Memory: API
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 4
• Isp: SPI/OCD/UART
• Watchdog: Yes

Table 5-1.
36
Symbol
MRW
SMLB
SMLA
CBE1
CBE0
MVCD
DPRB
DSPR = E2H
Not Bit Addressable
Bit
1-0
AT89LP51RD2/ED2/ID2 Preliminary
Function
M Register Window. Selects which pair of bytes from the 5-byte M register is accessible through MACH (E5H) and
MACL (E4H) as shown in
order portion of the fractional result is discarded.
Signed Multiply Operand B. When SMLB = 0, the MUL AB instruction treats the contents of B as an unsigned value.
When SMLB = 1, the MUL AB instruction interprets the contents of B as a signed two’s complement value. SMLB does
not affect the MAC operation.
Signed Multiply Operand A. When SMLA = 0, the MUL AB instruction treats the contents of ACC as an unsigned value.
When SMLA = 1, the MUL AB instruction interprets the contents of ACC as a signed two’s complement value. SMLA
does not affect the MAC operation.
DPTR1 Circular Buffer Enable. Set CBE1 = 1 to configure DPTR1 for circular addressing over the two circular buffer
address ranges. Clear CBE1 for normal DPTR operation.
DPTR0 Circular Buffer Enable. Set CBE0 = 1 to configure DPTR0 for circular addressing over the two circular buffer
address ranges. Clear CBE0 for normal DPTR operation.
MOVC Index Disable. When MVCD = 0, the MOVC A, @A+DPTR instruction functions normally with indexed
addressing. Setting MVCD = 1 disables the indexed addressing mode such that MOVC A, @A+DPTR functions as
MOVC A, @DPTR.
DPTR1 Redirect to B. DPRB selects the source/destination register for MOVC/MOVX instructions that reference DPTR1.
When DPRB = 0, ACC is the source/destination. When DPRB = 1, B is the source/destination. DPRB does not change
the index register for MOVC instructions.
DSPR
MRW1
7
– Digital Signal Processing Configuration Register
Figure 5-4.
As a consequence of the MAC unit, the standard 8x8 MUL AB instruction can support signed
multiplication. The SMLA and SMLB bits in DSPR control the multiplier’s interpretation of the
ACC and B registers, allowing any combination of signed and unsigned operand multiplication.
These bits have no effect on the MAC operation which always multiplies signed-by-signed.
MRW0
6
Figure
M
M Register with Sliding Window
SMLB
5-4. For example, MRW = 10B for normal 16-bit fixed-point operations where the lowest
5
39 – 32
MACH
Byte 4
SMLA
31 – 24
MACH
4
MACL
Byte 3
CBE1
23 – 16
MACH
MACL
Byte 2
3
CBE0
MACH
15 – 8
MACL
Byte 1
2
Reset Value = 0000 0000B
MVCD
MACL
7 – 0
Byte 0
1
MRW
MRW
MRW
MRW
DPRB
1-0
1-0
1-0
1-0
3714A–MICRO–7/11
= 00B
= 01B
= 10B
= 11B
0