AT89LP51ED2 Atmel Corporation, AT89LP51ED2 Datasheet - Page 5

• Manufacturer Part Number: AT89LP51ED2
• Manufacturer: Atmel Corporation

Specifications of AT89LP51ED2

• Flash (kbytes): 64 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 42
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Adc Channels: 7
• Adc Resolution (bits): 10
• Adc Speed (ksps): 153.8
• Sram (kbytes): 2.25
• Eeprom (bytes): 4096
• Self Program Memory: API
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 4
• Isp: SPI/OCD/UART
• Watchdog: Yes

Table 1-1.
3714A–MICRO–7/11
VQFP
VQFN
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
Pin Number
PLCC
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Atmel AT89LP51RD2/ED2/ID2 Pin Description
PDIP
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
(1)
Symbol
GND
P4.3
P2.0
P2.1
P2.1
P2.3
P2.4
P2.5
P2.6
P2.7
P4.5
P4.4
P4.0
POL
P0.7
P0.6
P0.5
P0.4
P0.3
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
Description
Ground
P4.3: User-configurable I/O Port 4bit 3.
DDA: Bidirectional Debug Data line for the On-Chip Debug Interface when OCD is enabled.
P2.0: User-configurable I/O Port 2 bit 0.
A8: External memory interface Address bit 8.
P2.1: User-configurable I/O Port 2 bit 1.
A9: External memory interface Address bit 9.
P2.2: User-configurable I/O Port 2 bit 2.
DA-: DAC negative differential output.
A10: External memory interface Address bit 10.
P2.3: User-configurable I/O Port 2 bit 3.
DA+-: DAC positive differential output.
A11: External memory interface Address bit 11.
P2.4: User-configurable I/O Port 2 bit 5.
AIN0: Analog Comparator Input 0.
A12: External memory interface Address bit 12.
P2.5: User-configurable I/O Port 2 bit 5.
AIN1: Analog Comparator Input 1.
A13: External memory interface Address bit 13.
P2.6: User-configurable I/O Port 2 bit 6.
AIN2: Analog Comparator Input 2.
A14: External memory interface Address bit 14.
P2.7: User-configurable I/O Port 2 bit 7.
AIN3: Analog Comparator Input 3.
A15: External memory interface Address bit 15.
P4.5: User-configurable I/O Port 4 bit 5.
PSEN: External memory interface Program Store Enable (active-low).
P4.4: User-configurable I/O Port 4 bit 4.
ALE: External memory interface Address Latch Enable.
P4.0: User-configurable I/O Port 4 bit 0.
SCL: TWI Serial Clock line. This line is an output in mater mode and an input in slave mode.
POL: Reset polarity
P0.7: User-configurable I/O Port 0 bit 7.
AD7: External memory interface Address/Data bit 7.
P0.6: User-configurable I/O Port 0 bit 6.
AD6: External memory interface Address/Data bit 6.
ADC6: ADC analog input 6.
P0.5: User-configurable I/O Port 0 bit 5.
AD5: External memory interface Address/Data bit 5.
ADC5: ADC analog input 5.
P0.4: User-configurable I/O Port 0 bit 4.
AD4: External memory interface Address/Data bit 4.
ADC4: ADC analog input 4.
P0.3: User-configurable I/O Port 0 bit 3.
AD3: External memory interface Address/Data bit 3.
ADC3: ADC analog input 3.
AT89LP51RD2/ED2/ID2 Preliminary
(See “External Reset” on page
55.)
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