AT89LP51ED2 Atmel Corporation, AT89LP51ED2 Datasheet - Page 6

• Manufacturer Part Number: AT89LP51ED2
• Manufacturer: Atmel Corporation

Specifications of AT89LP51ED2

• Flash (kbytes): 64 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 42
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Adc Channels: 7
• Adc Resolution (bits): 10
• Adc Speed (ksps): 153.8
• Sram (kbytes): 2.25
• Eeprom (bytes): 4096
• Self Program Memory: API
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 4
• Isp: SPI/OCD/UART
• Watchdog: Yes

Table 1-1.
Note:
2. Overview
6
VQFN
VQFP
35
36
37
38
39
40
41
42
43
44
Pin Number
1. The AT89LP51ID2 is not available in the PDIP package
PLCC
AT89LP51RD2/ED2/ID2 Preliminary
41
42
43
44
1
2
3
4
5
6
Atmel AT89LP51RD2/ED2/ID2 Pin Description
PDIP
37
38
39
40
(1)
1
2
3
4
5
Symbol
The Atmel
controller with 64KB of In-System Programmable Flash program memory. The AT89LP51ED2
and AT89LP51ID2 provide an additional 4KB of EEPROM for nonvolatile data storage. The
devices are manufactured using Atmel's high-density nonvolatile memory technology and are
compatible with the industry-standard 80C51 instruction set.
The AT89LP51RD2/ED2/ID2 is built around an enhanced CPU core that can fetch a single byte
from memory every clock cycle. In the classic 8051 architecture, each fetch requires 6 clock
c y c l e s , f o r c i n g i n s t r u c t i o n s t o e x e c u t e i n 1 2 , 2 4 o r 4 8 c l o c k c y c l e s . I n t h e
AT89LP51RD2/ED2/ID2 CPU, standard instructions need only one to four clock cycles providing
six to twelve times more throughput than the standard 8051. Seventy percent of instructions
need only as many clock cycles as they have bytes to execute, and most of the remaining
instructions require only one additional clock. The enhanced CPU core is capable of 20 MIPS
throughput whereas the classic 8051 CPU can deliver only 4 MIPS at the same current con-
sumption. Conversely, at the same throughput as the classic 8051, the new CPU core runs at a
much lower speed and thereby greatly reducing power consumption and EMI. The
VDD
P0.2
P0.1
P0.0
P4.2
P1.0
P1.1
P1.2
P1.3
P1.4
Type
®
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
I
I
AT89LP51RD2/ED2/ID2 is a low-power, high-performance CMOS 8-bit 8051 micro-
Description
P0.2: User-configurable I/O Port 0 bit 2.
AD2: External memory interface Address/Data bit 2.
ADC2: ADC analog input 2.
P0.1: User-configurable I/O Port 0 bit 1.
AD1: External memory interface Address/Data bit 1.
ADC1: ADC analog input 1.
P0.0: User-configurable I/O Port 0 bit 0.
AD0: External memory interface Address/Data bit 0.
ADC0: ADC analog input 0.
Supply Voltage
P4.2: User-configurable I/O Port 4bit 2.
XTAL2B: Output from low-frequency inverting oscillator amplifier B (AT89LP51ID2 only). It may
be used as a port pin if the internal RC oscillator or external clock is selected as the clock source
B.
P1.0: User-configurable I/O Port 1 bit 0.
T2: Timer 2 External Input or Clock Output.
XTAL1B: Input to the low-frequency inverting oscillator amplifier B and internal clock generation
circuits. It may be used as a port pin if the internal RC oscillator is selected as the clock source
B.
P1.1: User-configurable I/O Port 1 bit 1.
T2EX: Timer 2 External Capture/Reload Input.
SS: SPI Slave-Select.
P1.2: User-configurable I/O Port 1 bit 2.
P1.3: User-configurable I/O Port 1 bit 3.
CEX0: Capture/Compare external I/O for PCA module 0.
P1.4: User-configurable I/O Port 1 bit 4.
SS: SPI Slave-Select (Remap Mode). This pin is an input for In-System Programming
CEX1: Capture/Compare external I/O for PCA module 1.
3714A–MICRO–7/11