AT89LP51ED2 Atmel Corporation, AT89LP51ED2 Datasheet - Page 73
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AT89LP51ED2
Manufacturer Part Number
AT89LP51ED2
Description
Manufacturer
Atmel Corporation
Specifications of AT89LP51ED2
Flash (kbytes)
64 Kbytes
Max. Operating Frequency
20 MHz
Cpu
8051-1C
Max I/o Pins
42
Spi
1
Twi (i2c)
1
Uart
1
Adc Channels
7
Adc Resolution (bits)
10
Adc Speed (ksps)
153.8
Sram (kbytes)
2.25
Eeprom (bytes)
4096
Self Program Memory
API
Operating Voltage (vcc)
2.4 to 5.5
Timers
4
Isp
SPI/OCD/UART
Watchdog
Yes
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12.1.2
3714A–MICRO–711
Input-only Mode
A second pull-up, called the “weak” pull-up, is turned on when the port latch for the pin contains
a logic “1” and the pin itself is also at a logic “1” level. This pull-up provides the primary source
current for a quasi-bidirectional pin that is outputting a “1”. If this pin is pulled low by an external
device, this weak pull-up turns off, and only the very weak pull-up remains on. In order to pull the
pin low under these conditions, the external device has to sink enough current to overpower the
weak pull-up and pull the port pin below its input threshold voltage.
The third pull-up is referred to as the “strong” pull-up. This pull-up is used to speed up low-to-
high transitions on a quasi-bidirectional port pin when the port latch changes from a logic “0” to a
logic “1”. When this occurs, the strong pull-up turns on for one CPU clock, quickly pulling the port
pin high. The quasi-bidirectional port configuration is shown in
The input only port configuration is shown in
input includes a Schmitt-triggered input for improved input noise rejection. The input circuitry of
P3.2, P3.3, P4.6 and P4.7 is not disabled during Power-down (see
these pins should not be left floating during Power-down when configured in this mode.
Input-only mode can reduce power consumption for low-level inputs over quasi-bidirectional
mode because the “very weak” pull-up is turned off and only very small leakage current in the
sub microamp range is present.
Figure 12-1. Quasi-bidirectional Output
Figure 12-2. Input Only
Figure 12-3. Input Circuit for P3.2, P3.3, P4.6 and P4.7
F rom P o r t
Register
Input
Data
Input
AT89LP51RD2/ED2/ID2 Preliminary
Data
1 Clo c k Del a y
(D Flip-Flop)
PWD
Figure
Input
Data
PWD
12-2. The output drivers are tristated. The
V
Strong
CC
Figure
P o r t
Port
Pin
Pin
V
W ea k
V e r y
CC
Figure
12-1.
V
W ea k
CC
12-3) and therefore
P o r t
Pin
73
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