AT90CAN64 Atmel Corporation, AT90CAN64 Datasheet - Page 212

• Manufacturer Part Number: AT90CAN64
• Manufacturer: Atmel Corporation

Specifications of AT90CAN64

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 8
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 2
• Can: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 8
• Input Capture Channels: 2
• Pwm Channels: 7
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

18.6
18.6.1
18.6.2
212
TWI Register Description
AT90CAN32/64/128
TWI Bit Rate Register – TWBR
TWI Control Register – TWCR
• Bits 7.0 – TWI Bit Rate Register
TWBR selects the division factor for the bit rate generator. The bit rate generator is a frequency
divider which generates the SCL clock frequency in the Master modes. See
Unit” on page 210
The TWCR is used to control the operation of the TWI. It is used to enable the TWI, to initiate a
master access by applying a START condition to the bus, to generate a receiver acknowledge,
to generate a stop condition, and to control halting of the bus while the data to be written to the
bus are written to the TWDR. It also indicates a write collision if data is attempted written to
TWDR while the register is inaccessible.
• Bit 7 – TWINT: TWI Interrupt Flag
This bit is set by hardware when the TWI has finished its current job and expects application
software response. If the I-bit in SREG and TWIE in TWCR are set, the MCU will jump to the
TWI interrupt vector. While the TWINT flag is set, the SCL low period is stretched. The TWINT
flag must be cleared by software by writing a logic one to it. Note that this flag is not automati-
cally cleared by hardware when executing the interrupt routine. Also note that clearing this flag
starts the operation of the TWI, so all accesses to the TWI Address Register (TWAR), TWI Sta-
tus Register (TWSR), and TWI Data Register (TWDR) must be complete before clearing this
flag.
• Bit 6 – TWEA: TWI Enable Acknowledge Bit
The TWEA bit controls the generation of the ACK pulse. If the TWEA bit is written to one, the
ACK pulse is generated on the TWI bus if the following conditions are met:
By writing the TWEA bit to zero, the device can be virtually disconnected from the Two-wire
Serial Bus temporarily. Address recognition can then be resumed by writing the TWEA bit to one
again.
• Bit 5 – TWSTA: TWI START Condition Bit
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
• When a bus error has occurred due to an illegal START or STOP condition
1. The device’s own slave address has been received.
2. A general call has been received, while the TWGCE bit in the TWAR is set.
3. A data byte has been received in Master Receiver or Slave Receiver mode.
TWBR7
TWINT
R/W
R/W
7
0
7
0
for calculating bit rates.
TWBR6
TWEA
R/W
R/W
6
0
6
0
TWBR5
TWSTA
R/W
R/W
5
0
5
0
TWBR4
TWSTO
R/W
R/W
4
0
4
0
TWBR3
TWWC
R/W
3
0
3
R
0
TWBR2
TWEN
R/W
R/W
2
0
2
0
TWBR1
R/W
R
1
0
1
–
0
TWBR0
TWIE
R/W
R/W
0
0
0
0
“Bit Rate Generator
TWBR
TWCR
7679H–CAN–08/08