AT90CAN64 Atmel Corporation, AT90CAN64 Datasheet - Page 307

• Manufacturer Part Number: AT90CAN64
• Manufacturer: Atmel Corporation

Specifications of AT90CAN64

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 8
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 2
• Can: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 8
• Input Capture Channels: 2
• Pwm Channels: 7
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

23.6.3
23.6.4
7679H–CAN–08/08
Scanning the RESET Pin
Scanning the Clock Pins
Figure 23-5. Additional Scan Signal for the Two-wire Interface
The RESET pin accepts 3V or 5V active low logic for standard reset operation, and 12V active
high logic for High Voltage Parallel programming. An observe-only cell as shown in
is inserted both for the 3V or 5V reset signal - RSTT, and the 12V reset signal - RSTHV.
Figure 23-6. Observe-only Cell for RESET pin
The AVR devices have many clock options selectable by fuses. These are: Internal RC Oscilla-
tor, External Clock, (High Frequency) Crystal Oscillator, Low-frequency Crystal Oscillator, and
Ceramic Resonator.
Figure 23-7
The Enable signal is supported with a general Boundary-scan cell, while the Oscillator/clock out-
put is attached to an observe-only cell. In addition to the main clock, the Timer2 Oscillator is
scanned in the same way. The output from the internal RC Oscillator is not scanned, as this
oscillator does not have external connections.
shows how each oscillator with external connection is supported in the scan chain.
Pxn
From System Pin
Previous
From
Cell
ShiftDR
0
1
ClockDR
D
FF1
Slew-rate limited
Q
AT90CAN32/64/128
Next
Cell
To
SRC
To System Logic
OCxn
ODxn
TWIEN
IDxn
PUExn
Figure 23-6
307