AT90CAN64 Atmel Corporation, AT90CAN64 Datasheet - Page 417

• Manufacturer Part Number: AT90CAN64
• Manufacturer: Atmel Corporation

Specifications of AT90CAN64

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 8
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 2
• Can: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 8
• Input Capture Channels: 2
• Pwm Channels: 7
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

7679H–CAN–08/08
Let’s consider 4 sections in the Flash, described below:
Table 33-1.
Failing cases :
7. CAN acknowledge error in 3-sample mode with prescaler =1
6. CAN transmission after 3-bit intermission
Bootsize=4096 Words
Bootsize=2048 Words
Bootsize=1024 Words
Bootsize=512 Words
LPM instruction
LPM instruction
LPM instruction
LPM instruction
Problem fix / workaround
If protection level 3 is mandatory, the LPM instruction must be moved outside the failing
sections.
Some acknowledge errors can occur when the clock prescaler = 1 (BRP[5..0] = 0 in
CANBTR1 register) and the SMP bit is set (CANBTR3[0] = 1 in CANBTR3 register). That
can result in a reduction of the maximum length of the CAN bus.
Problem fix / workaround
If BRP[5..0]=0 use SMP=0.
If a Transmit Message Object (MOb) is enabled while the CAN bus is busy with an on going
message, the transmitter will wait for the 3-bit intermission before starting its transmission.
This is in full agreement with the CAN recommendation.
If the transmitter lost arbitration against another node, two conditions can occur:
- At least one receive MOb of the chip are programmed to accept the incoming message. In
- No receive MOb of the chip are programmed to accept the incoming message. In this case
Problem fix / workaround
Always have a receive MOb enabled ready to accept any incoming messages. Thanks to
the implementation of the CAN interface, a receive MOb must be enable at latest, before the
1
immediately after the 6th bit of the End of Frame field. This will leave in CAN2.0A mode a
minimum 19-bit time delay to respond to the end of message interrupt (RXOK) and re-
enable the receive MOb before the start of the DLC field of the next incoming message. This
st
this case, the transmitter will wait for the next 3-bit intermission to retry its transmission.
the transmitter will wait for a 4-bit intermission to retry its transmission. In this case, any
other CAN nodes ready to transmit after a 3-bit intermission will start transmit before the
chip transmitter, even if their messages have lower priority IDs.
bit of the DLC field. The receive MOb status register is written (RXOK if message OK)
Flash memory sections
From memory
space
D
B
B
A or C
T o me meo ry
space
B
D
B
A or C
M e m o r y
s p a c e
Application
0000h-2FFFh
0000h-37FFh
0000h-3BFFh
0000h-3DFFh
A
:
Bug comment
Allowed but should not be valid
Allowed but should not be valid
Not allowed but should be
Not allowed but should be
M e m o r y
s p a c e
Application
3000h-3FFFh
3800h-3FFFh
3C00h-3FFFh
3E00h-3FFFh
B
:
AT90CAN32/64/128
M e m o r y
s p a c e
Application
4000h-6FFFh
4000h-77FFh
4000h-7BFFh
4000h-7DFFh
C
:
M e m o r y
s p a c e
Bootloader
7000h-7FFFh
7800h-7FFFh
7C00h-7FFFh
7E00h-7FFFh
D
:
417