AT90CAN64 Atmel Corporation, AT90CAN64 Datasheet - Page 314
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AT90CAN64
Manufacturer Part Number
AT90CAN64
Description
Manufacturer
Atmel Corporation
Specifications of AT90CAN64
Flash (kbytes)
64 Kbytes
Pin Count
64
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
53
Ext Interrupts
8
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Uart
2
Can
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
4
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
4
Output Compare Channels
8
Input Capture Channels
2
Pwm Channels
7
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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23.7
314
AT90CAN32/64/128 Boundary-scan Order
AT90CAN32/64/128
The recommended values from
rithm in
“Actions” describes what JTAG instruction to be used before filling the Boundary-scan Register
with the succeeding columns. The verification should be done on the data scanned out when
scanning in the data on the same row in the table.
Table 23-8.
Using this algorithm, the timing constraint on the HOLD signal constrains the TCK clock fre-
quency. As the algorithm keeps HOLD high for five steps, the TCK clock frequency has to be at
least five times the number of scan bits divided by the maximum hold time, t
Table 23-9
selected as data path. Bit 0 is the LSB; the first bit scanned in, and the first bit scanned out. The
scan order follows the pin-out order as far as possible. Therefore, the bits of Port A is scanned in
the opposite bit order of the other ports. Exceptions from the rules are the Scan chains for the
analog circuits, which constitute the most significant bits of the scan chain regardless of which
physical pin they are connected to. In
Step
1
2
3
4
5
6
7
8
9
10
11
Table
Actions
SAMPLE_
PRELOAD
EXTEST
Verify the
COMP bit
scanned out
to be 0
Verify the
COMP bit
scanned out
to be 1
shows the Scan order between TDI and TDO when the Boundary-scan chain is
23-8. Only the DAC and port pin values of the Scan Chain are shown. The column
Algorithm for Using the ADC
ADCEN
1
1
1
1
1
1
1
1
1
1
1
DAC
0x200
0x200
0x200
0x123
0x123
0x200
0x200
0x200
0x143
0x143
0x200
Table 23-7
Figure
MUXEN
0x08
0x08
0x08
0x08
0x08
0x08
0x08
0x08
0x08
0x08
0x08
are used unless other values are given in the algo-
23-3, PXn. Data corresponds to FF0, PXn. Control
HOLD
1
0
1
1
1
1
0
1
1
1
1
PRECH
1
1
1
1
0
1
1
1
1
0
1
PA3.
Data
0
0
0
0
0
0
0
0
0
0
0
hold,max
PA3.
Control
0
0
0
0
0
0
0
0
0
0
0
7679H–CAN–08/08
PA3.
Pullup_
Enable
0
0
0
0
0
0
0
0
0
0
0