AT90PWM3B Atmel Corporation, AT90PWM3B Datasheet - Page 128
AT90PWM3B
Manufacturer Part Number
AT90PWM3B
Description
Manufacturer
Atmel Corporation
Specifications of AT90PWM3B
Flash (kbytes)
8 Kbytes
Pin Count
32
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
8
Hardware Qtouch Acquisition
No
Max I/o Pins
27
Ext Interrupts
4
Usb Speed
No
Usb Interface
No
Spi
1
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
10
Adc Speed (ksps)
125
Analog Comparators
3
Resistive Touch Screen
No
Dac Channels
1
Dac Resolution (bits)
10
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
0.5
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 105
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
5
Output Compare Channels
16
Input Capture Channels
1
Pwm Channels
12
32khz Rtc
No
Calibrated Rc Oscillator
Yes
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128
AT90PWM2/3/2B/3B
Timer/Counter1 Interrupt Flag Register – TIFR1
Interrupt Vector (see “Reset and Interrupt Vectors Placement in AT90PWM2/2B/3/3B(1)” on
page 57) is executed when the OCF1A Flag, located in TIFR1, is set.
• Bit 0 – TOIE1: Timer/Counter1, Overflow Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Overflow interrupt is enabled. The corresponding Interrupt Vector
(see “Reset and Interrupt Vectors Placement in AT90PWM2/2B/3/3B(1)” on page 57) is exe-
cuted when the TOV1 Flag, located in TIFR1, is set.
• Bit 7, 6 – Res: Reserved Bits
These bits are unused bits in the AT90PWM2/2B/3/3B, and will always read as zero.
• Bit 5 – ICF1: Timer/Counter1, Input Capture Flag
This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture Register
(ICR1) is set by the WGMn3:0 to be used as the TOP value, the ICF1 Flag is set when the coun-
ter reaches the TOP value.
ICF1 is automatically cleared when the Input Capture Interrupt Vector is executed. Alternatively,
ICF1 can be cleared by writing a logic one to its bit location.
• Bit 4, 3 – Res: Reserved Bits
These bits are unused bits in the AT90PWM2/2B/3/3B, and will always read as zero.
• Bit 2 – OCF1B: Timer/Counter1, Output Compare B Match Flag
This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output
Compare Register B (OCR1B).
Note that a Forced Output Compare (FOC1B) strobe will not set the OCF1B Flag.
OCF1B is automatically cleared when the Output Compare Match B Interrupt Vector is exe-
cuted. Alternatively, OCF1B can be cleared by writing a logic one to its bit location.
• Bit 1 – OCF1A: Timer/Counter1, Output Compare A Match Flag
This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output
Compare Register A (OCR1A).
Note that a Forced Output Compare (FOC1A) strobe will not set the OCF1A Flag.
OCF1A is automatically cleared when the Output Compare Match A Interrupt Vector is exe-
cuted. Alternatively, OCF1A can be cleared by writing a logic one to its bit location.
• Bit 0 – TOV1: Timer/Counter1, Overflow Flag
The setting of this flag is dependent of the WGMn3:0 bits setting. In Normal and CTC modes,
the TOV1 Flag is set when the timer overflows. Refer to
Flag behavior when using another WGMn3:0 bit setting.
TOV1 is automatically cleared when the Timer/Counter1 Overflow Interrupt Vector is executed.
Alternatively, TOV1 can be cleared by writing a logic one to its bit location.
Bit
Read/Write
Initial Value
R
7
–
0
R
6
–
0
ICF1
R/W
5
0
R
4
–
0
R
3
–
0
Table 15-5 on page 124
OCF1B
R/W
2
0
OCF1A
R/W
1
0
TOV1
R/W
0
0
4317J–AVR–08/10
for the TOV1
TIFR1
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