AT90PWM3B Atmel Corporation, AT90PWM3B Datasheet - Page 129
AT90PWM3B
Manufacturer Part Number
AT90PWM3B
Description
Manufacturer
Atmel Corporation
Specifications of AT90PWM3B
Flash (kbytes)
8 Kbytes
Pin Count
32
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
8
Hardware Qtouch Acquisition
No
Max I/o Pins
27
Ext Interrupts
4
Usb Speed
No
Usb Interface
No
Spi
1
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
10
Adc Speed (ksps)
125
Analog Comparators
3
Resistive Touch Screen
No
Dac Channels
1
Dac Resolution (bits)
10
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
0.5
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 105
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
5
Output Compare Channels
16
Input Capture Channels
1
Pwm Channels
12
32khz Rtc
No
Calibrated Rc Oscillator
Yes
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16. Power Stage Controller – (PSC0, PSC1 & PSC2)
16.1
16.2
4317J–AVR–08/10
Features
Overview
The Power Stage Controller is a high performance waveform controller.
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Many register and bit references in this section are written in general form.
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The purpose of a Power Stage Controller (PSC) is to control power modules on a board. It has
two outputs on PSC0 and PSC1 and four outputs on PSC2.
These outputs can be used in various ways:
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Each PSC has two inputs the purpose of which is to provide means to act directly on the gener-
ated waveforms:
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The PSC can be chained and synchronized to provide a configuration to drive three half bridges.
Thanks to this feature it is possible to generate a three phase waveforms for applications such
as Asynchronous or BLDC motor drive.
PWM waveform generation function (2 complementary programmable outputs)
Dead time control
Standard mode up to 12 bit resolution
Frequency Resolution Enhancement Mode (12 + 4 bits)
Frequency up to 64 Mhz
Conditional Waveform on External Events (Zero Crossing, Current Sensing ...)
All on chip PSC synchronization
ADC synchronization
Overload protection function
Abnormality protection function, emergency input to force all outputs to high impedance or in
inactive state (fuse configurable)
Center aligned and edge aligned modes synchronization
Fast emergency stop by hardware
A lower case “n” replaces the PSC number, in this case 0, 1 or 2. However, when using the
register or bit defines in a program, the precise form must be used, i.e., PSOC1 for
accessing PSC 0 Synchro and Output Configuration register and so on.
A lower case “x” replaces the PSC part , in this case A or B. However, when using the
register or bit defines in a program, the precise form must be used, i.e., PFRCnA for
accessing PSC n Fault/Retrigger n A Control register and so on.
“Two Ouputs” to drive a half bridge (lighting, DC motor ...)
“One Output” to drive single power transistor (DC/DC converter, PFC, DC motor ...)
“Four Outputs” in the case of PSC2 to drive a full bridge (lighting, DC motor ...)
Current sensing regulation
Zero crossing retriggering
Demagnetization retriggering
Fault input
AT90PWM2/3/2B/3B
129
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