AT90PWM3B Atmel Corporation, AT90PWM3B Datasheet - Page 165
AT90PWM3B
Manufacturer Part Number
AT90PWM3B
Description
Manufacturer
Atmel Corporation
Specifications of AT90PWM3B
Flash (kbytes)
8 Kbytes
Pin Count
32
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
8
Hardware Qtouch Acquisition
No
Max I/o Pins
27
Ext Interrupts
4
Usb Speed
No
Usb Interface
No
Spi
1
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
10
Adc Speed (ksps)
125
Analog Comparators
3
Resistive Touch Screen
No
Dac Channels
1
Dac Resolution (bits)
10
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
0.5
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 105
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
5
Output Compare Channels
16
Input Capture Channels
1
Pwm Channels
12
32khz Rtc
No
Calibrated Rc Oscillator
Yes
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16.25.12 PSC 1 Control Register – PCTL1
4317J–AVR–08/10
• Bit 7:6 – PPRE01:0 : PSC 0 Prescaler Select
This two bits select the PSC input clock division factor. All generated waveform will be modified
by this factor.
Table 16-14. PSC 0 Prescaler Selection
• Bit 5 – PBFM0 : Balance Flank Width Modulation
When this bit is clear, Flank Width Modulation operates on On-Time 1 only.
When this bit is set, Flank Width Modulation operates on On-Time 0 and On-Time 1.
• Bit 4 – PAOC0B : PSC 0 Asynchronous Output Control B
When this bit is set, Fault input selected to block B can act directly to PSCOUT01 output. See
Section “PSC Input Configuration”, page 146.
• Bit 3 – PAOC0A : PSC 0 Asynchronous Output Control A
When this bit is set, Fault input selected to block A can act directly to PSCOUT00 output. See
Section “PSC Input Configuration”, page 146.
• Bit 2 – PARUN0 : PSC 0 Autorun
When this bit is set, the PSC 0 starts with PSC2. That means that PSC 0 starts :
•
•
Thanks to this bit, 2 or 3 PSCs can be synchronized (motor control for example)
• Bit 1 – PCCYC0 : PSC 0 Complete Cycle
When this bit is set, the PSC 0 completes the entire waveform cycle before halt operation
requested by clearing PRUN0. This bit is not relevant in slave mode (PARUN0 = 1).
• Bit 0 – PRUN0 : PSC 0 Run
Writing this bit to one starts the PSC 0.
When set, this bit prevails over PARUN0 bit.
Bit
Read/Write
Initial Value
PPRE01
0
0
1
1
when PRUN2 bit in PCTL2 is set,
or when PARUN2 bit in PCTL2 is set and PRUN1 bit in PCTL1 register is set.
PPRE00
0
1
0
1
PPRE11
R/W
7
0
PPRE10
R/W
6
0
Description PWM2/3
No divider on PSC input clock
Divide the PSC input clock by 4
Divide the PSC input clock by 16
Divide the PSC clock by 64
PBFM1
R/W
5
0
PAOC1B
R/W
4
0
PAOC1A
R/W
3
0
AT90PWM2/3/2B/3B
PARUN1
R/W
Description PWM2B/3B
No divider on PSC input clock
Divide the PSC input clock by 4
Divide the PSC input clock by 32
Divide the PSC clock by 256
2
0
PCCYC1
R/W
1
0
PRUN1
R/W
0
0
PCTL1
165
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