ATmega16HVB Atmel Corporation, ATmega16HVB Datasheet - Page 142
ATmega16HVB
Manufacturer Part Number
ATmega16HVB
Description
Manufacturer
Atmel Corporation
Specifications of ATmega16HVB
Flash (kbytes)
16 Kbytes
Pin Count
44
Max. Operating Frequency
8 MHz
Cpu
8-bit AVR
# Of Touch Channels
8
Hardware Qtouch Acquisition
No
Max I/o Pins
17
Ext Interrupts
15
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
12
Adc Speed (ksps)
1.9
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
1
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
4.0 to 25
Operating Voltage (vcc)
4.0 to 25
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
4
Input Capture Channels
2
32khz Rtc
No
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATmega16HVB-8X3
Manufacturer:
LT
Quantity:
51
Part Number:
ATmega16HVB-8X3
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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24.7.8
24.7.9
24.7.10
142
ATmega16HVB/32HVB
BPCOCD – Battery Protection Charge-Over-current Detection Level Register
BPDHCD – Battery Protection Discharge-High-current Detection Level Register
BPCHCD – Battery Protection Charge-High-current Detection Level Register
• Bits 7:0 –COCDL[7:0]: Charge Over-current Detection Level
These bits sets the R
Table
Note:
• Bits 7:0 – DHCDL[7:0]: Discharge High-current Detection Level
These bits sets the R
Table
Note:
• Bits 7:0 –CHCDL[7:0]: Charge High-current Detection Level
These bits sets the R
Table
Note:
Table 24-5.
Bit
(0xF7)
Read/Write
Initial Value
Bit
(0xF8)
Read/Write
Initial Value
Bit
(0xF9)
Read/Write
Initial Value
24-5.
24-5.
24-5.
Due to synchronization of parameters between clock domains, a guard time of three ULP oscilla-
tor cycles plus three CPU clock cycles is required between each time the BPCOCD register is
written. Any writing to the BPCOCD register during this period will be ignored.
Due to synchronization of parameters between clock domains, a guard time of three ULP oscilla-
tor cycles plus three CPU clock cycles is required between each time the BPDHCD register is
written. Any writing to the BPDHCD register during this period will be ignored.
Due to synchronization of parameters between clock domains, a guard time of three ULP oscilla-
tor cycles plus three CPU clock cycles is required between each time the BPCHCD register is
written. Any writing to the BPCHCD register during this period will be ignored.
DL[7:0] with corresponding R
registers (BPSCD, BPDOCD, BPCOCD, BPDHCD, BPCHCD).
R/W
R/W
R/W
7
1
7
1
7
1
DL[7:0]
0xF3
0xF4
0xF5
SENSE
SENSE
SENSE
R/W
R/W
R/W
6
1
6
1
6
1
voltage level for detection of DischargeHigh-current, as defined in
voltage level for detection of Charge Over-current, as defined in
voltage level for detection of Charge High-current, as defined in
Current protection detection levels
R/W
R/W
R/W
5
1
5
1
5
1
R/W
R/W
R/W
SENSE
4
1
4
1
4
1
COCDL[7:0]
DHCDL[7:0]
CHCDL[7:0]
voltage levels for all current detection level
R/W
R/W
R/W
3
0
3
0
3
0
R/W
R/W
R/W
2
0
2
0
2
0
Typical (mV)
R/W
R/W
R/W
20
25
30
1
1
1
1
1
1
R/W
R/W
R/W
0
1
0
1
0
1
8042D–AVR–10/11
BPDHCD
BPCOCD
BPCHCD
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