ATmega16HVB Atmel Corporation, ATmega16HVB Datasheet - Page 152
ATmega16HVB
Manufacturer Part Number
ATmega16HVB
Description
Manufacturer
Atmel Corporation
Specifications of ATmega16HVB
Flash (kbytes)
16 Kbytes
Pin Count
44
Max. Operating Frequency
8 MHz
Cpu
8-bit AVR
# Of Touch Channels
8
Hardware Qtouch Acquisition
No
Max I/o Pins
17
Ext Interrupts
15
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
12
Adc Speed (ksps)
1.9
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
1
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
4.0 to 25
Operating Voltage (vcc)
4.0 to 25
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
4
Input Capture Channels
2
32khz Rtc
No
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATmega16HVB-8X3
Manufacturer:
LT
Quantity:
51
Part Number:
ATmega16HVB-8X3
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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26.2
26.2.1
152
Register description
ATmega16HVB/32HVB
CBCR – Cell Balancing Control Register
• Bit 7:4 – Reserved
These bits are reserved in the Atmel ATmega16HVB/32HVB and will always read as zero.
• Bit 3 – CBE4: Cell Balancing Enable 4
When this bit is set, the integrated Cell Balancing FET between terminals PV4 and PV3 will be
enabled. When the bit is cleared, the Cell Balancing FET will be disabled. The Cell Balancing
FETs are always disabled in Power-off mode. CBE4 cannot be set if CBE3 is set.
• Bit 2 – CBE3: Cell Balancing Enable 3
When this bit is set, the integrated Cell Balancing FET between terminals PV3 and PV2 will be
enabled. When the bit is cleared, the Cell Balancing FET will be disabled. The Cell Balancing
FETs are always disabled in Power-off mode. CBE3 cannot be set if CBE2 or CBE4 is set.
• Bit 1 – CBE2: Cell Balancing Enable 2
When this bit is set, the integrated Cell Balancing FET between terminals PV2 and PV1 will be
enabled. When the bit is cleared, the Cell Balancing FET will be disabled. The Cell Balancing
FETs are always disabled in Power-off mode. CBE2 cannot be set if CBE1 or CBE3 is set.
• Bit 0 – CBE1: Cell Balancing Enable 1
When this bit is set (one), the integrated Cell Balancing FET between terminals PV1 and NV will
be enabled. When the bit is cleared (zero), the Cell Balancing FET will be disabled. The Cell Bal-
ancing FETs are always disabled in Power-off mode. CBE1 cannot be set if CBE2 is set.
Bit
(0xF1)
Read/Write
Initial Value
R
7
–
0
R
6
–
0
R
5
–
0
R
4
–
0
CBE4
R/W
3
0
CBE3
R/W
2
0
CBE2
R/W
1
0
CBE1
R/W
0
0
8042D–AVR–10/11
CBCR
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