ATmega16HVB Atmel Corporation, ATmega16HVB Datasheet - Page 38

• Manufacturer Part Number: ATmega16HVB
• Manufacturer: Atmel Corporation

Specifications of ATmega16HVB

• Flash (kbytes): 16 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 8 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 8
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 17
• Ext Interrupts: 15
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 1.9
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 1
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 4.0 to 25
• Operating Voltage (vcc): 4.0 to 25
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Input Capture Channels: 2
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

10.5
10.6
10.7
10.7.1
10.7.2
38
Power-off mode
Power Reduction Register
Minimizing power consumption
ATmega16HVB/32HVB
Watchdog Timer
Port pins
If the current through the sense resistor is so small that the Coulomb Counter cannot measure it
accurately, Regular Current detection should be enabled to reduce power consumption. The
WDT keeps accurately track of the time so that battery self discharge can be calculated.
Note that if a level triggered interrupt is used for wake-up from Power-save mode, the changed
level must be held for some time to wake up the MCU. Refer to
for details.
When waking up from Power-save mode, there is a delay from the wake-up condition occurs
until the wake-up becomes effective. This allows the clock to restart and become stable after
having been stopped. The wake-up period is defined in
When the SM2..0 bits are written to 100 and the SE bit is set, the SLEEP instruction makes the
CPU shut down the Voltage Regulator, leaving only the Charger Detect Circuitry operational. To
ensure that the MCU enters Power-off mode only when intended, the SLEEP instruction must be
executed within 4 clock cycles after the SM2..0 bits are written. The MCU will reset when return-
ing from Power-off mode.
Note:
The Power Reduction Register (PRR), see
provides a method to stop the clock to individual peripherals to reduce power consumption. The
current state of the peripheral is frozen and the I/O registers can not be read or written.
Resources used by the peripheral when stopping the clock will remain occupied, hence the
peripheral should in most cases be disabled before stopping the clock. Waking up a module,
which is done by clearing the bit in PRR, puts the module in the same state as before shutdown.
Module shutdown can be used in Idle mode and Active mode to significantly reduce the overall
power consumption. In all other sleep modes, the clock is already stopped.
There are several issues to consider when trying to minimize the power consumption in an AVR
controlled system. In general, sleep modes should be used as much as possible, and the sleep
mode should be selected so that as few as possible of the device’s functions are operating. All
functions not needed should be disabled. In particular, the following modules may need special
consideration when trying to achieve the lowest possible power consumption.
If the Watchdog Timer is not needed in the application, the module should be turned off. If the
Watchdog Timer is enabled, it will be enabled in all sleep modes except Power-off. The Watch-
dog Timer current consumption is significant only in Power-save mode. Refer to
timer” on page 46
When entering a sleep mode, all port pins should be configured to use minimum power. The
most important is then to ensure that no pins drive resistive loads. In sleep modes where both
the I/O clock (clk
be disabled. This ensures that no power is consumed by the input logic when not needed. In
1. Before entering Power-off sleep mode, interrupts should be disabled by software. Otherwise
interrupts may prevent the SLEEP instruction from being executed within the time limit.
I/O
for details on how to configure the Watchdog Timer.
) and the ADC clock (clk
ADC
”PRR0 – Power Reduction Register 0” on page
) are stopped, the input buffers of the device will
”Clock sources” on page
”External interrupts” on page 58
26.
8042D–AVR–10/11
”Watchdog
40,