ATmega16U4 Atmel Corporation, ATmega16U4 Datasheet - Page 20
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ATmega16U4
Manufacturer Part Number
ATmega16U4
Description
Manufacturer
Atmel Corporation
Specifications of ATmega16U4
Flash (kbytes)
16 Kbytes
Pin Count
44
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
14
Hardware Qtouch Acquisition
No
Max I/o Pins
26
Ext Interrupts
13
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
2
Twi (i2c)
1
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
2.1
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
4
Output Compare Channels
12
Input Capture Channels
2
Pwm Channels
8
32khz Rtc
No
Calibrated Rc Oscillator
Yes
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5.2.1
7766F–AVR–11/10
Data Memory Access Times
The Indirect with Displacement mode reaches 63 address locations from the base address given
by the Y- or Z-register.
When using register indirect addressing modes with automatic pre-decrement and post-incre-
ment, the address registers X, Y, and Z are decremented or incremented.
The 32 general purpose working registers, 64 I/O registers, and the 1.25/2.5Kbytes of internal
data SRAM in the ATmega16U4/ATmega32U4 are all accessible through all these addressing
modes. The Register File is described in
Figure 5-2.
This section describes the general access timing concepts for internal memory access. The
internal data SRAM access is performed in two clk
Figure 5-3.
Address
clk
Data Memory Map
On-chip Data SRAM Access Cycles
Data
Data
WR
CPU
RD
64 I/O
D ata M emory
160 E xt I/O
I nternal S RAM
32 R egisters
Compute Address
R egisters
T1
Memory Access Instruction
R eg .
“General Purpose Register File” on page
$FFFF
$0000 - $001F
$0020 - $005F
$0060 - $00FF
ISRAM start : $0100
Address valid
ISRAM end : $05FF / $0AFF
CPU
T2
cycles as described in
ATmega16/32U4
Next Instruction
T3
Figure
12.
5-3.
20
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