ATmega16U4 Atmel Corporation, ATmega16U4 Datasheet - Page 86
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ATmega16U4
Manufacturer Part Number
ATmega16U4
Description
Manufacturer
Atmel Corporation
Specifications of ATmega16U4
Flash (kbytes)
16 Kbytes
Pin Count
44
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
14
Hardware Qtouch Acquisition
No
Max I/o Pins
26
Ext Interrupts
13
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
2
Twi (i2c)
1
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
2.1
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
4
Output Compare Channels
12
Input Capture Channels
2
Pwm Channels
8
32khz Rtc
No
Calibrated Rc Oscillator
Yes
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11.0.2
7766F–AVR–11/10
External Interrupt Control Register B – EICRB
Table 11-1.
Note:
Table 11-2.
• Bit 7..6 – Res: Reserved Bits
These bits are reserved bits in the ATmega16U4/ATmega32U4 and always read as zero.
• Bits 5, 4 – ISC61, ISC60: External Interrupt 6 Sense Control Bits
The External Interrupt 6 is activated by the external pin INT6 if the SREG I-flag and the corre-
sponding interrupt mask in the EIMSK is set. The level and edges on the external pin that
activate the interrupt are defined in
detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock
period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt.
Observe that CPU clock frequency can be lower than the XTAL frequency if the XTAL divider is
enabled. If low level interrupt is selected, the low level must be held until the completion of the
currently executing instruction to generate an interrupt. If enabled, a level triggered interrupt will
generate an interrupt request as long as the pin is held low.
Table 11-3.
Note:
Bit
Read/Write
Initial Value
Symbol
ISCn1
ISC61
t
0
0
1
1
0
0
1
1
INT
1. n = 3, 2, 1or 0.
1. When changing the ISC61/ISC60 bits, the interrupt must be disabled by clearing its Interrupt
ISC60
ISCn0
When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by clearing its Interrupt
Enable bit in the EIMSK Register. Otherwise an interrupt can occur when the bits are changed.
Enable bit in the EIMSK Register. Otherwise an interrupt can occur when the bits are changed.
Parameter
Minimum pulse width for
asynchronous external interrupt
0
1
0
1
0
1
0
1
7
-
R/W
0
Asynchronous External Interrupt Characteristics
Interrupt Sense Control
Interrupt Sense Control
Description
The low level of INT6 generates an interrupt request.
Any logical change on INT6 generates an interrupt request
The falling edge between two samples of INT6 generates an interrupt
request.
The rising edge between two samples of INT6 generates an interrupt
request.
Description
The low level of INTn generates an interrupt request.
Any edge of INTn generates asynchronously an interrupt request.
The falling edge of INTn generates asynchronously an interrupt request.
The rising edge of INTn generates asynchronously an interrupt request.
6
-
R/W
0
5
ISC61
R/W
0
Table
4
ISC60
R/W
0
(1)
(1)
11-3. The value on the INT6 pin are sampled before
3
-
0
R/W
Condition
2
-
R/W
0
Min
1
-
R/W
0
ATmega16/32U4
Typ
50
0
-
R/W
0
Max
EICRB
Units
ns
86
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