ATmega2561R212 Atmel Corporation, ATmega2561R212 Datasheet - Page 351
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ATmega2561R212
Manufacturer Part Number
ATmega2561R212
Description
Manufacturer
Atmel Corporation
Specifications of ATmega2561R212
Flash (kbytes)
256 Kbytes
Max. Operating Frequency
16 MHz
Max I/o Pins
54
Spi
3
Twi (i2c)
1
Uart
2
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Crypto Engine
AES
Sram (kbytes)
8
Eeprom (bytes)
4096
Operating Voltage (vcc)
1.8 to 3.6
Timers
6
Frequency Band
700/800/900MHz
Max Data Rate (mb/s)
1
Antenna Diversity
No
External Pa Control
Yes
Power Output (dbm)
10
Receiver Sensitivity (dbm)
-110
Receive Current Consumption (ma)
9.0
Transmit Current Consumption (ma)
18 at 5dBm
Link Budget (dbm)
120
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2549N–AVR–05/11
To program and verify the ATmega640/1280/1281/2560/2561 in the serial programming mode,
the following sequence is recommended (see four byte instruction formats in
page
1. Power-up sequence:
2. Wait for at least 20ms and enable serial programming by sending the Programming
3. The serial programming instructions will not work if the communication is out of synchro-
4. The Flash is programmed one page at a time. The memory page is loaded one byte at a
5. The EEPROM array is programmed one byte at a time by supplying the address and data
6. Any memory location can be verified by using the Read instruction which returns the con-
7. At the end of the programming session, RESET can be set high to commence normal
8. Power-off sequence (if needed):
Table 30-16. Minimum Wait Delay Before Writing the Next Flash or EEPROM Location
Symbol
t
t
t
WD_FLASH
WD_EEPROM
WD_ERASE
Apply power between V
tems, the programmer can not guarantee that SCK is held low during power-up. In this
case, RESET must be given a positive pulse of at least two CPU clock cycles duration
after SCK has been set to “0”.
Enable serial instruction to pin PDI.
nization. When in sync. the second byte (0x53), will echo back when issuing the third
byte of the Programming Enable instruction. Whether the echo is correct or not, all four
bytes of the instruction must be transmitted. If the 0x53 did not echo back, give RESET a
positive pulse and issue a new Programming Enable command.
time by supplying the 7 LSB of the address and data together with the Load Program
Memory Page instruction. To ensure correct loading of the page, the data low byte must
be loaded before data high byte is applied for a given address. The Program Memory
Page is stored by loading the Write Program Memory Page instruction with the address
lines 15:8. Before issuing this command, make sure the instruction Load Extended
Address Byte has been used to define the MSB of the address. The extended address
byte is stored until the command is re-issued, that is, the command needs only be issued
for the first page, and when crossing the 64KWord boundary. If polling (
used, the user must wait at least t
16). Accessing the serial programming interface before the Flash write operation com-
pletes can result in incorrect programming.
together with the appropriate Write instruction. An EEPROM memory location is first
automatically erased before new data is written. If polling is not used, the user must wait
at least t
device, no 0xFFs in the data file(s) need to be programmed.
tent at the selected address at serial output PDO. When reading the Flash memory, use
the instruction Load Extended Address Byte to define the upper address byte, which is
not included in the Read Program Memory instruction. The extended address byte is
stored until the command is re-issued, that is, the command needs only be issued for the
first page, and when crossing the 64KWord boundary.
operation.
Set RESET to “1”.
Turn V
352):
CC
WD_EEPROM
power off.
before issuing the next byte (see
CC
and GND while RESET and SCK are set to “0”. In some sys-
ATmega640/1280/1281/2560/2561
WD_FLASH
before issuing the next page (see
Minimum Wait Delay
Table
4.5ms
3.6ms
9.0ms
30-16). In a chip erased
RDY/BSY
Table 30-17 on
Table 30-
) is not
351
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