ATmega325 Atmel Corporation, ATmega325 Datasheet - Page 22

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ATmega325

Manufacturer Part Number
ATmega325
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATmega325

Flash (kbytes)
32 Kbytes
Pin Count
64
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
54
Ext Interrupts
17
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
1
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
2
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
4
Input Capture Channels
1
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

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8.5
8.5.1
8.5.2
8.5.3
2570N–AVR–05/11
Register Description
EEARH and EEARL – The EEPROM Address Register
EEDR – The EEPROM Data Register
EECR – The EEPROM Control Register
• Bits 15:11 – Reserved Bits
These bits are reserved bits in the Atmel ATmega325/3250/645/6450 and will always read as
zero.
• Bits 10:0 – EEAR10:0: EEPROM Address
The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address in the
1/2K bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and
1023/2047. The initial value of EEAR is undefined. A proper value must be written before the
EEPROM may be accessed.
Note:
• Bits 7:0 – EEDR7..0: EEPROM Data
For the EEPROM write operation, the EEDR Register contains the data to be written to the
EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the
EEDR contains the data read out from the EEPROM at the address given by EEAR.
• Bits 7:4 – Reserved Bits
These bits are reserved bits in the Atmel ATmega325/3250/645/6450 and will always read as
zero.
• Bit 3 – EERIE: EEPROM Ready Interrupt Enable
Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing
EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant inter-
rupt when EEWE is cleared.
Bit
0x22 (0x42)
0x21 (0x41)
Read/Write
Initial Value
Bit
0x20 (0x40)
Read/Write
Initial Value
Bit
0x1F (0x3F)
Read/Write
Initial Value
EEAR10 is only valid for ATmega645 and ATmega6450.
EEAR7
MSB
R/W
R/W
15
R
X
7
0
7
0
R
7
0
EEAR6
R/W
R/W
14
R
6
0
X
6
0
R
6
0
EEAR5
R/W
R/W
13
R
X
5
0
5
0
R
5
0
EEAR4
R/W
R/W
12
R
X
4
0
4
0
R
4
0
ATmega325/3250/645/6450
EEAR3
EERIE
R/W
R/W
R/W
11
R
3
0
X
3
0
3
0
EEAR10
EEMWE
EEAR2
R/W
R/W
R/W
R/W
10
X
X
2
2
0
2
0
EEAR9
EEAR1
EEWE
R/W
R/W
R/W
R/W
X
X
X
9
1
1
0
1
EEAR8
EEAR0
EERE
R/W
R/W
LSB
R/W
R/W
X
X
8
0
0
0
0
0
EEARH
EEARL
EEDR
EECR
22

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