ATmega325 Atmel Corporation, ATmega325 Datasheet - Page 228

• Manufacturer Part Number: ATmega325
• Manufacturer: Atmel Corporation

Specifications of ATmega325

• Flash (kbytes): 32 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 54
• Ext Interrupts: 17
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 2
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

25.5.2
25.6
25.6.1
2570N–AVR–05/11
Boundary-scan Chain
MCUSR – MCU Status Register
Scanning the Digital Port Pins
software must write this bit to the desired value twice within four cycles to change its value. Note
that this bit must not be altered when using the On-chip Debug system.
If the JTAG interface is left unconnected to other JTAG circuitry, the JTD bit should be set to
one. The reason for this is to avoid static current at the TDO pin in the JTAG interface.
The MCU Status Register provides information on which reset source caused an MCU reset.
• Bit 4 – JTRF: JTAG Reset Flag
This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by
the JTAG instruction AVR_RESET. This bit is reset by a Power-on Reset, or by writing a logic
zero to the flag.
The Boundary-scan chain has the capability of driving and observing the logic levels on the digi-
tal I/O pins, as well as the boundary between digital and analog logic for analog circuitry having
off-chip connection.
Figure 25-3
cell consists of a standard Boundary-scan cell for the Pull-up Enable – PUExn – function, and a
bi-directional pin cell that combines the three signals Output Control – OCxn, Output Data –
ODxn, and Input Data – IDxn, into only a two-stage Shift Register. The port and pin indexes are
not used in the following description
The Boundary-scan logic is not included in the figures in the Data Sheet.
simple digital port pin as described in the section
details from
When no alternate port function is present, the Input Data – ID – corresponds to the PINxn Reg-
ister value (but ID has no synchronizer), Output Data corresponds to the PORT Register, Output
Control corresponds to the Data Direction – DD Register, and the Pull-up Enable – PUExn – cor-
responds to logic expression PUD · DDxn · PORTxn.
Digital alternate port functions are connected outside the dotted box in
scan chain read the actual pin value. For Analog function, there is a direct connection from the
external pin to the analog circuit, and a scan chain is inserted on the interface between the digi-
tal logic and the analog circuitry.
Bit
0x34 (0x54)
Read/Write
Initial Value
shows the Boundary-scan Cell for a bi-directional port pin with pull-up function. The
Figure 25-3
R
7
–
0
R
replaces the dashed box in
6
–
0
R
5
–
0
JTRF
R/W
4
ATmega325/3250/645/6450
WDRF
R/W
3
“I/O-Ports” on page
See Bit Description
Figure
BORF
R/W
2
25-4.
EXTRF
R/W
1
Figure 25-4
60. The Boundary-scan
PORF
R/W
0
Figure 25-4
MCUSR
to make the
shows a
228