ATmega325 Atmel Corporation, ATmega325 Datasheet - Page 35

• Manufacturer Part Number: ATmega325
• Manufacturer: Atmel Corporation

Specifications of ATmega325

• Flash (kbytes): 32 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 54
• Ext Interrupts: 17
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 2
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

10. Power Management and Sleep Modes
10.1
Table 10-1.
Note:
10.2
2570N–AVR–05/11
Sleep Mode
Idle
ADC Noise
Reduction
Power-down
Power-save
Standby
Sleep Modes
1. Only recommended with external crystal or resonator selected as clock source.
2. If Timer/Counter2 is running in asynchronous mode.
3. For INT0, only level interrupt.
Idle Mode
(1)
Active Clock Domains and Wake-up Sources in the Different Sleep Modes.
Active Clock Domains
Sleep modes enable the application to shut down unused modules in the MCU, thereby saving
power. The AVR provides various sleep modes allowing the user to tailor the power consump-
tion to the application’s requirements.
F i g u r e 9 - 1 o n p a g e 2 6
ATmega325/3250/645/6450, and their distribution. The figure is helpful in selecting an appropri-
ate sleep mode.
sources.
To enter any of the five sleep modes, the SE bit in SMCR must be written to logic one and a
SLEEP instruction must be executed. The SM2, SM1, and SM0 bits in the SMCR Register select
which sleep mode (Idle, ADC Noise Reduction, Power-down, Power-save, or Standby) will be
activated by the SLEEP instruction. See
If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU
is then halted for four cycles in addition to the start-up time, executes the interrupt routine, and
resumes execution from the instruction following SLEEP. The contents of the Register File and
SRAM are unaltered when the device wakes up from sleep. If a reset occurs during sleep mode,
the MCU wakes up and executes from the Reset Vector.
When the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle
mode, stopping the CPU but allowing the SPI, USART, Analog Comparator, ADC, USI,
Timer/Counters, Watchdog, and the interrupt system to continue operating. This sleep mode
basically halts clk
Idle mode enables the MCU to wake up from external triggered interrupts as well as internal
ones like the Timer Overflow and USART Transmit Complete interrupts. If wake-up from the
X
X
X
CPU
Table 10-1 on page 35
X
X
X
and clk
FLASH
X
X
X
Oscillators
p r e s e n t s t h e d i f f e r e n t c l o c k s y s t e m s i n t h e A t m e l
, while allowing the other clocks to run.
X
X
X
Table 10-2 on page 39
(2)
(2)
(2)
shows the different sleep modes and their wake up
ATmega325/3250/645/6450
X
X
X
X
X
(3)
(3)
(3)
(3)
X
X
X
X
X
Wake-up Sources
for a summary.
X
X
X
(2)
X
X
X
X
X
35