ATmega325 Atmel Corporation, ATmega325 Datasheet - Page 70

• Manufacturer Part Number: ATmega325
• Manufacturer: Atmel Corporation

Specifications of ATmega325

• Flash (kbytes): 32 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 54
• Ext Interrupts: 17
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 2
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 4
• Input Capture Channels: 1
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

2570N–AVR–05/11
Table 14-4
shown in
MISO signal, while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT.
Table 14-4.
Table 14-5.
Signal
Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
PTOE
DIEOE
DIEOV
DI
AIO
Signal
Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
PTOE
DIEOE
DIEOV
DI
AIO
Figure 14-5 on page
and
Overriding Signals for Alternate Functions in PB7:PB4
Overriding Signals for Alternate Functions in PB3:PB0
PB7/OC2A/
PCINT15
0
0
0
0
OC2A ENABLE
OC2A
–
PCINT15 •
PCIE1
1
PCINT15 INPUT
–
PB3/MISO/
PCINT11
SPE • MSTR
PORTB3 • PUD
SPE • MSTR
0
SPE • MSTR
SPI SLAVE
OUTPUT
–
PCINT11 •
PCIE1
1
PCINT11 INPUT
SPI MSTR
INPUT
–
Table 14-5
relate the alternate functions of Port B to the overriding signals
66. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute the
PB6/OC1B/
PCINT14
0
0
0
0
OC1B ENABLE
OC1B
–
PCINT14 •
PCIE1
1
PCINT14 INPUT
–
PB2/MOSI/
PCINT10
SPE • MSTR
PORTB2 • PUD
SPE • MSTR
0
SPE • MSTR
SPI MSTR
OUTPUT
–
PCINT10 •
PCIE1
1
PCINT10 INPUT
SPI SLAVE
INPUT
–
ATmega325/3250/645/6450
PB5/OC1A/
PCINT13
0
0
0
0
OC1A ENABLE
OC1A
–
PCINT13 •
PCIE1
1
PCINT13 INPUT
–
PB1/SCK/
PCINT9
SPE • MSTR
PORTB1 • PUD
SPE • MSTR
0
SPE • MSTR
SCK OUTPUT
–
PCINT9 • PCIE1
1
PCINT9 INPUT
SCK INPUT
–
PB4/OC0A/
PCINT12
0
0
0
0
OC0A ENABLE
OC0A
–
PCINT12 •
PCIE1
1
PCINT12 INPUT
–
PB0/SS/
PCINT8
SPE • MSTR
PORTB0 • PUD
SPE • MSTR
0
0
0
–
PCINT8 • PCIE1
1
PCINT8 INPUT
SPI SS
–
70