ATmega32U4 Atmel Corporation, ATmega32U4 Datasheet - Page 169
ATmega32U4
Manufacturer Part Number
ATmega32U4
Description
Manufacturer
Atmel Corporation
Specifications of ATmega32U4
Flash (kbytes)
32 Kbytes
Pin Count
44
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
14
Hardware Qtouch Acquisition
No
Max I/o Pins
26
Ext Interrupts
13
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
2
Twi (i2c)
1
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
12
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
3.3
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
4
Output Compare Channels
12
Input Capture Channels
2
Pwm Channels
8
32khz Rtc
No
Calibrated Rc Oscillator
Yes
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15.12.5
7766F–AVR–11/10
TCCR4E – Timer/Counter4 Control Register E
• Bit 3 - FPAC4: Fault Protection Analog Comparator Enable
When written logic one, this bit enables the Fault Protection function in Timer/Counter4 to be
triggered by the Analog Comparator. The comparator output is in this case directly connected to
the Fault Protection front-end logic, making the comparator utilize the noise canceler and edge
select features of the Timer/Counter4 Fault Protection interrupt. When written logic zero, no con-
nection between the Analog Comparator and the Fault Protection function exists. To make the
comparator trigger the Timer/Counter4 Fault Protection interrupt, the FPIE4 bit in the
Timer/Counter4 Control Register D (TCCR4D) must be set.
• Bit 2- FPF4: Fault Protection Interrupt Flag
When the FPIE4 bit is set (one), the Fault Protection Interrupt is enabled. Activity on the pin will
cause an interrupt request even, if the Fault Protection pin is configured as an output. The corre-
sponding interrupt of Fault Protection Interrupt Request is executed from the Fault Protection
Interrupt Vector. The bit FPF4 is cleared by hardware when executing the corresponding inter-
rupt handling vector. Alternatively, FPF4 is cleared after a synchronization clock cycle by writing
a logical one to the flag. When the SREG I-bit, FPIE4 and FPF4 are set, the Fault Interrupt is
executed.
• Bits 1:0 - WGM41, WGM40: Waveform Generation Mode Bits
This bit associated with the PWM4x bits control the counting sequence of the counter, the
source for type of waveform generation to be used, see
ported by the Timer/Counter4 are: Normal mode (counter), Fast PWM Mode, Phase and
Frequency Correct PWM and PWM6 Modes.
Table 15-19. Waveform Generation Mode Bit Description
• Bit 7 - TLOCK4: Register Update Lock
This bit controls the Compare registers update. When this bit is set, writing to the Compare reg-
isters will not affect the output, however the values are stored and will be updated to the
Compare registers when the TLOCK4 bit will be cleared.
Refer to
Bit
Read/Write
Initial value
PWM4x
0
1
1
1
1
Section 15.7 ”Synchronous update” on page 149
WGM41..40
TLOCK4
00
01
10
11
xx
R
7
0
ENHC4
Timer/Counter Mode of Operation
Normal
Fast PWM
Phase and Frequency Correct PWM
PWM6 / Single-slope
PWM6 / Dual-slope
R
6
0
OC4OE5
R/W
5
0
OC4OE4
R/W
4
0
OC4OE3
R/W
3
0
Table
for more details.
OC4OE2
TOP
OCR4C
OCR4C
OCR4C
OCR4C
OCR4C
R/W
2
0
15-19. Modes of operation sup-
ATmega16/32U4
OC4OE1
R/W
1
0
Update of
OCR4x at
Immediate
TOP
BOTTOM
TOP
BOTTOM
OC4OE0
R/W
0
0
TOV4 Flag
Set on
TOP
TOP
BOTTOM
TOP
BOTTOM
TCCR4E
169
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