ATmega32U4 Atmel Corporation, ATmega32U4 Datasheet - Page 170

• Manufacturer Part Number: ATmega32U4
• Manufacturer: Atmel Corporation

Specifications of ATmega32U4

• Flash (kbytes): 32 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 14
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 26
• Ext Interrupts: 13
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 12
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 3.3
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 12
• Input Capture Channels: 2
• Pwm Channels: 8
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

15.12.6
15.12.7
7766F–AVR–11/10
TCNT4 – Timer/Counter4
TC4H – Timer/Counter4 High Byte
• Bit 6- ENHC4: Enhanced Compare/PWM Mode
When this bit is set, the Waveform Generation Module works in enhanced mode: the compare
registers OCR4A/B/D can welcome one more accuracy bit, while the LSB determines on which
clock edge the Compare condition is signalled and the output pin level is updated.
• Bits 5:0 – OC4OE5:OC4OE0: Output Compare Override Enable Bits
These bits are the Output Compare Override Enable bits that are used to connect or disconnect
the Output Compare Pins in PWM6 Modes with an instant response on the corresponding Out-
put Compare Pins. The actual value from the port register will be visible on the port pin, when
the Output Compare Override Enable Bit is cleared.
Override Enable Bits and their corresponding Output Compare pins.
Table 15-20. Output Compare Override Enable Bits vs. Output Compare Pins
This 8-bit register contains the value of Timer/Counter4.
The Timer/Counter4 is realized as a 10-bit up/down counter with read and write access. Due to
synchronization of the CPU, Timer/Counter4 data written into Timer/Counter4 is delayed by one
and half CPU clock cycles in synchronous mode and at most one CPU clock cycles for asyn-
chronous mode. When a 10-bit accuracy is preferred, special procedures must be followed for
accessing the 10-bit TCNT4 register via the 8-bit AVR data bus. These procedures are
described in section
can be used as an 8-bit Timer/Counter. Note that the Timer/Counter4 always starts counting up
after writing the TCNT4 register.
The temporary Timer/Counter4 register is an 2-bit read/write register.
• Bits 7:3- Res: Reserved Bits
These bits are reserved bits in the ATmega16U4/ATmega32U4 and always reads as zero.
• Bits 2- TC410: Additional MSB bits for 11-bit accesses in Enhanced PWM mode
If 10-bit accuracy is used, the Timer/Counter4 High Byte Register (TC4H) is used for temporary
storing the MSB bits (TC49, TC48) of the 10-bit accesses. The same TC4H register is shared
between all 10-bit registers within the Timer/Counter4. Note that special procedures must be fol-
lowed when accessing the 10-bit TCNT4 register via the 8-bit AVR data bus. These procedures
are described in section
OC4OE0
OC4A
Bit
4
Read/Write
Initial value
Bit
Read/Write
Initial value
(PC6)
MSB
R/W
OC4OE1
OC4A
R
7
0
7
0
-
“Accessing 10-Bit Registers” on page
(PC7)
“Accessing 10-Bit Registers” on page
R/W
R
6
0
6
0
-
OC4OE2
OC4B
R/W
R
5
0
5
0
-
(PB5)
R/W
R
4
0
4
0
-
OC4OE3
OC4B
R/W
R
3
0
3
0
-
Table 15-20
(PB6)
159. Alternatively the Timer/Counter4
TC410
R/W
159.
R
2
0
2
0
OC4OE4
OC4D
ATmega16/32U4
shows the Output Compare
TC49
(PD6)
R/W
R/W
1
0
1
0
TC48
LSB
R/W
R/W
OC4OE5
OC4D
0
0
0
0
(PD7)
TCNT4
TC4H
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