ATmega88 Atmel Corporation, ATmega88 Datasheet - Page 14
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ATmega88
Manufacturer Part Number
ATmega88
Description
Manufacturer
Atmel Corporation
Specifications of ATmega88
Flash (kbytes)
8 Kbytes
Pin Count
32
Max. Operating Frequency
20 MHz
Cpu
8-bit AVR
# Of Touch Channels
12
Hardware Qtouch Acquisition
No
Max I/o Pins
23
Ext Interrupts
24
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
1
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
1
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
6
Input Capture Channels
1
Pwm Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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7.6.1
7.7
2545T–AVR–05/11
Instruction execution timing
SPH and SPL – Stack pointer high and stack pointer low register
This section describes the general access timing concepts for instruction execution. The AVR
CPU is driven by the CPU clock clk
chip. No internal clock division is used.
Figure 7-4
vard architecture and the fast-access Register File concept. This is the basic pipelining concept
to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost,
functions per clocks, and functions per power-unit.
Figure 7-4.
Figure 7-5
operation using two register operands is executed, and the result is stored back to the destina-
tion register.
Figure 7-5.
Bit
0x3E (0x5E)
0x3D (0x5D)
Read/write
Initial value
Register operands fetch
2nd instruction execute
ALU operation execute
3rd instruction execute
1st instruction execute
2nd instruction fetch
Total execution time
3rd instruction fetch
4th instruction fetch
1st instruction fetch
Result write back
shows the internal timing concept for the Register File. In a single clock cycle an ALU
shows the parallel instruction fetches and instruction executions enabled by the Har-
RAMEND
RAMEND
SP15
The parallel instruction fetches and instruction executions.
Single cycle ALU operation.
SP7
R/W
R/W
15
7
clk
clk
CPU
CPU
RAMEND
RAMEND
SP14
SP6
R/W
R/W
14
6
RAMEND
RAMEND
SP13
R/W
R/W
SP5
13
5
CPU
T1
T1
, directly generated from the selected clock source for the
RAMEND
RAMEND
SP12
R/W
R/W
SP4
12
4
RAMEND
RAMEND
SP11
R/W
R/W
SP3
T2
T2
11
3
RAMEND
RAMEND
SP10
ATmega48/88/168
SP2
R/W
R/W
10
2
T3
T3
RAMEND
RAMEND
SP9
SP1
R/W
R/W
9
1
RAMEND
RAMEND
SP8
SP0
R/W
R/W
8
0
T4
T4
SPH
SPL
14