ATmega88 Atmel Corporation, ATmega88 Datasheet - Page 209
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ATmega88
Manufacturer Part Number
ATmega88
Description
Manufacturer
Atmel Corporation
Specifications of ATmega88
Flash (kbytes)
8 Kbytes
Pin Count
32
Max. Operating Frequency
20 MHz
Cpu
8-bit AVR
# Of Touch Channels
12
Hardware Qtouch Acquisition
No
Max I/o Pins
23
Ext Interrupts
24
Usb Speed
No
Usb Interface
No
Spi
2
Twi (i2c)
1
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
1
Eeprom (bytes)
512
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8 to 5.5
Operating Voltage (vcc)
1.8 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
6
Input Capture Channels
1
Pwm Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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22. 2-wire serial interface
22.1
22.2
22.2.1
2545T–AVR–05/11
Features
2-wire serial interface bus definition
TWI terminology
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The 2-wire Serial Interface (TWI) is ideally suited for typical microcontroller applications. The
TWI protocol allows the systems designer to interconnect up to 128 different devices using only
two bi-directional bus lines, one for clock (SCL) and one for data (SDA). The only external hard-
ware needed to implement the bus is a single pull-up resistor for each of the TWI bus lines. All
devices connected to the bus have individual addresses, and mechanisms for resolving bus
contention are inherent in the TWI protocol.
Figure 22-1. TWI bus interconnection.
The following definitions are frequently encountered in this section.
Table 22-1.
Term
Master
Simple yet powerful and flexible communication interface, only two bus lines needed
Both master and slave operation supported
Device can operate as transmitter or receiver
7-bit address space allows up to 128 different slave addresses
Multi-master arbitration support
Up to 400kHz data transfer speed
Slew-rate limited output drivers
Noise suppression circuitry rejects spikes on bus lines
Fully programmable slave address with general call support
Address recognition causes wake-up when AVR is in sleep mode
Compatible with Philips I
SDA
SCL
TWI terminology.
Description
The device that initiates and terminates a transmission. The master also generates the
SCL clock.
Device 1
2
C protocol
Device 2
Device 3
........
Device n
V
ATmega48/88/168
CC
R1
R2
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