ATmega88 Atmel Corporation, ATmega88 Datasheet - Page 67

• Manufacturer Part Number: ATmega88
• Manufacturer: Atmel Corporation

Specifications of ATmega88

• Flash (kbytes): 8 Kbytes
• Pin Count: 32
• Max. Operating Frequency: 20 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 12
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 23
• Ext Interrupts: 24
• Usb Speed: No
• Usb Interface: No
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 1
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8 to 5.5
• Operating Voltage (vcc): 1.8 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 3
• Output Compare Channels: 6
• Input Capture Channels: 1
• Pwm Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

13.2
13.2.1
2545T–AVR–05/11
Register description
EICRA – External interrupt control register A
The external interrupt control register A contains control bits for interrupt sense control.
• Bit 7..4 – Res: Reserved bits
These bits are unused bits in the Atmel ATmega48/88/168, and will always read as zero.
• Bit 3, 2 – ISC11, ISC10: Interrupt sense control 1 bit 1 and bit 0
The external interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corre-
sponding interrupt mask are set. The level and edges on the external INT1 pin that activate the
interrupt are defined in
edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will
generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level
interrupt is selected, the low level must be held until the completion of the currently executing
instruction to generate an interrupt.
Table 13-1.
• Bit 1, 0 – ISC01, ISC00: Interrupt sense control 0 bit 1 and bit 0
The external interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corre-
sponding interrupt mask are set. The level and edges on the external INT0 pin that activate the
interrupt are defined in
edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will
generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level
interrupt is selected, the low level must be held until the completion of the currently executing
instruction to generate an interrupt.
Table 13-2.
Bit
(0x69)
Read/write
Initial value
ISC11
ISC01
0
0
1
1
0
0
1
1
Interrupt 1 sense control.
Interrupt 0 sense control.
ISC10
ISC00
R
7
–
0
0
1
0
1
0
1
0
1
Table
Table
Description
Description
The low level of INT1 generates an interrupt request
Any logical change on INT1 generates an interrupt request
The falling edge of INT1 generates an interrupt request
The rising edge of INT1 generates an interrupt request
The low level of INT0 generates an interrupt request
Any logical change on INT0 generates an interrupt request
The falling edge of INT0 generates an interrupt request
The rising edge of INT0 generates an interrupt request
R
6
–
0
13-1. The value on the INT1 pin is sampled before detecting
13-2. The value on the INT0 pin is sampled before detecting
R
5
–
0
R
4
–
0
ISC11
R/W
3
0
ISC10
R/W
ATmega48/88/168
2
0
ISC01
R/W
1
0
ISC00
R/W
0
0
EICRA
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