ATxmega64A1 Atmel Corporation, ATxmega64A1 Datasheet - Page 308
ATxmega64A1
Manufacturer Part Number
ATxmega64A1
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega64A1
Flash (kbytes)
64 Kbytes
Pin Count
100
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
78
Ext Interrupts
78
Usb Speed
No
Usb Interface
No
Spi
12
Twi (i2c)
4
Uart
8
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
4
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
4
Eeprom (bytes)
2048
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
8
Output Compare Channels
24
Input Capture Channels
24
Pwm Channels
24
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATxmega64A1-AU
Manufacturer:
Atmel
Quantity:
135
Company:
Part Number:
ATxmega64A1U-AU
Manufacturer:
ATMEL
Quantity:
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25.16.10.1
25.16.10.2
25.16.10.3
25.16.11 CHnRESL - ADC Channel n Result register Low
25.16.11.1
25.16.11.2
25.16.12 CMPH - ADC Compare register High
8077H–AVR–12/09
12-bit mode, left adjusted
12-bit mode, right adjusted
8-bit mode
12-/8-bit mode
12-bit mode, left adjusted
• Bits 7:0 - CHRES[11:4]: ADC Channel Result, high byte
These are the 8 MSB of the 12-bit ADC result.
• Bits 7:4 - Reserved
These bits will in practice be the extension of the sign bit CHRES11 when ADC works in differen-
tial mode and set to zero when ADC works in signed mode.
• Bits 3:0 - CHRES[11:8]: ADC Channel Result, high byte
These are the 4 MSB of the 12-bit ADC result.
• Bits 7:0 - Reserved
These bits will in practice be the extension of the sign bit CHRES7 when ADC works in signed
mode and set to zero when ADC works in single-ended mode.
• Bits 7:0 - CHRES[7:0]: ADC Channel Result, low byte
These are the 8 LSB of the ADC result.
• Bits 7:4 - CHRES[3:0]: ADC Channel Result, low byte
These are the 4 LSB of the 12 bit ADC result.
• Bits 3:0 - Reserved
These bits are reserved and will always read as zero. For compatibility with future devices,
always write these bits to zero when this register is written.
The CMPH and CMPL register pair represents the 16-bit value ADC Compare (CMP). For
details on reading and writing 16-bit registers refer to
on page
12-/8-
12-bit, left
12.
Bit
Read/Write
Initial Value
R
7
0
R
6
0
CHRES[3:0]
R
5
0
Section 3.11 ”Accessing 16-bits Registers”
R
4
0
CHRES[7:0]
R
3
0
-
R
2
0
-
XMEGA A
R
1
0
-
R
0
0
-
308
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