ATxmega64B1 Atmel Corporation, ATxmega64B1 Datasheet - Page 126
ATxmega64B1
Manufacturer Part Number
ATxmega64B1
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega64B1
Flash (kbytes)
64 Kbytes
Pin Count
100
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
53
Ext Interrupts
53
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
1
Uart
2
Segment Lcd
160
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
8
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
10
Input Capture Channels
10
Pwm Channels
10
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATxmega64B1-AUR
Manufacturer:
ATMEL
Quantity:
210
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11.8.2
11.8.3
8291A–AVR–10/11
INTPRI – Interrupt priority register
CTRL – Control register
• Bit 7:0 – INTPRI: Interrupt Priority
When round-robin scheduling is enabled, this register stores the interrupt vector of the last
acknowledged low-level interrupt. The stored interrupt vector will have the lowest priority the
next time one or more low-level interrupts are pending. The register is accessible from software
to change the priority queue. This register is not reinitialized to its initial value if round-robing
scheduling is disabled, and so if default static priority is needed, the register must be written to
zero.
• Bit 7 – RREN: Round-robin Scheduling Enable
When the RREN bit is set, the round-robin scheduling scheme is enabled for low-level interrupts.
When this bit is cleared, the priority is static according to interrupt vector address, where the low-
est address has the highest priority.
• Bit 6 – IVSEL: Interrupt Vector Select
When the IVSEL bit is cleared (zero), the interrupt vectors are placed at the start of the applica-
tion section in flash. When this bit is set (one), the interrupt vectors are placed in the beginning
of the boot section of the flash. Refer to the device datasheet for the absolute address.
This bit is protected by the configuration change protection mechanism. Refer to
Change Protection” on page 12
• Bit 5:3 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 2 – HILVLEN: High-level Interrupt Enable
When this bit is set, all high-level interrupts are enabled. If this bit is cleared, high-level interrupt
requests will be ignored.
• Bit 1 – MEDLVLEN: Medium-level Interrupt Enable
When this bit is set, all medium-level interrupts are enabled. If this bit is cleared, medium-level
interrupt requests will be ignored.
Bit
+0x01
Read/Write
Initial Value
Bit
+0x02
Read/Write
Initial Value
RREN
R/W
R/W
7
0
7
0
IVSEL
R/W
R/W
6
0
6
0
for details.
R/W
R
5
–
0
5
0
R/W
R
4
–
0
4
0
INTPRI[7:0]
(1)
R/W
R
3
–
0
3
0
Atmel AVR XMEGA B
(1)
HILVLEN
R/W
R/W
2
0
2
0
MEDLVLEN
R/W
R/W
1
0
1
0
LOLVLEN
R/W
R/W
0
0
0
0
”Configuration
INTPRI
CTRL
126
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