ATxmega64B1 Atmel Corporation, ATxmega64B1 Datasheet - Page 313
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ATxmega64B1
Manufacturer Part Number
ATxmega64B1
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega64B1
Flash (kbytes)
64 Kbytes
Pin Count
100
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
53
Ext Interrupts
53
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
1
Uart
2
Segment Lcd
160
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
8
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
3
Output Compare Channels
10
Input Capture Channels
10
Pwm Channels
10
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATxmega64B1-AUR
Manufacturer:
ATMEL
Quantity:
210
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24.5.3
24.5.4
8291A–AVR–10/11
CTRLC – Control Register C
INTCTRL – Interrupt Enable Register
• Bit 3 – LPWAV: Low Power Waveform
When LPWAV is written to one, the low power waveform is outputted on LCD pins, otherwise the
standard waveform is outputted. If this bit is modified during display operation the change takes
place at the beginning of the next frame. (For more details see
306).
• Bit 2 – Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write
this bit to zero when this register is written.
• Bits 1:0 – DUTY[1:0]: Duty Select
The DUTY bit-field defines the duty cycle. Common pins that are not used will be driven to
ground. The different duty selections are shown in
Table 24-9.
Note:
• Bits 7:6 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bits 5:0 – PMSK[5:0]: LCD Port Mask
The PMSK bit-field defines the number of port pins to be used as segment drivers. The unused
pins will be driven to ground except the 16 highest pins which become GPIO's.
Bit
+0x03
Read/Write
Initial Value
Bit
+0x02
Read/Write
Initial Value
DUTY[1:0]
0 0
0 1
1 0
1 1
1. Refer to specific device datasheet for duty cycles availability (linked to the number of available
common terminals).
R/W
Duty selection
7
–
R
0
7
0
R/W
Static
Duty
R
6
–
0
6
0
1/4
1/2
1/3
XIME[4:0]
R/W
R/W
5
0
5
0
(1)
Static
Bias
1/3
1/3
1/3
R/W
R/W
4
0
4
0
Table 24-9 on page
R/W
R/W
3
0
3
0
PMSK[5:0]
Atmel AVR XMEGA B
COM pins Used
COM[0:3]
COM[0:1]
COM[0:2]
COM0
R/W
2
0
R
2
–
0
”Low Power Waveform” on page
313.
R/W
R/W
1
0
1
0
FCINTLVL[1:0]
R/W
R/W
0
0
0
0
INTCTRL
CTRLC
313
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