ATxmega64B3 Atmel Corporation, ATxmega64B3 Datasheet - Page 183

• Manufacturer Part Number: ATxmega64B3
• Manufacturer: Atmel Corporation

Specifications of ATxmega64B3

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 36
• Ext Interrupts: 36
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Segment Lcd: 100
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 2
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

14.10.3
14.10.4
14.10.5
8291A–AVR–10/11
CTRLC — Control register C
CTRLE — Control register E
INTCTRLA — Interrupt Enable register A
• Bit 7:0 – HCMPx/LCMPx: High/Low Compare x Output Value
These bits allow direct access to the waveform generator's output compare value when the
timer/counter is OFF. This is used to set or clear the WG output value when the timer/counter is
not running.
• Bit 7:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 0:1 – BYTEM[1:0]: Byte Mode
These bits select the timer/counter operation mode according to
Table 14-3.
• Bit 7:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
Bit
+0x04
Read/Write
Initial Value
Bit
+0x06
Read/Write
Initial Value
Bit
+0x02
Read/Write
Initial Value
CMD
00
01
10
11
HCMPD
R/W
7
–
R
0
Byte Mode
7
0
R
7
–
0
Group Configuration
SPLITMODE
BYTEMODE
NORMAL
HCMPC
R/W
R
6
–
0
6
0
R
6
–
0
—
HCMPB
R/W
R
5
–
0
R
5
0
5
–
0
Description
Timer/counter is set to normal mode (timer/counter type 0)
Upper byte of the counter (HCNT) will be set to zero after
each counter clock.
Timer/counter is split into two eight-bit timer/counters
(timer/counter type 2)
Reserved
HCMPA
R/W
R
4
0
4
–
0
R
4
–
0
LCMPD
R/W
R/W
HUNFINTLVL[1:0]
3
–
R
0
3
0
3
0
Atmel AVR XMEGA B
LCMPC
R/W
R/W
R
2
0
2
–
0
2
0
Table 14-3 on page
LCMPB
R/W
R/W
R/W
LUNFINTLVL[1:0]
1
0
1
0
1
0
BYTEM[1:0]
LCMPA
R/W
R/W
R/W
0
0
0
0
0
0
183.
INTCTRLA
CTRLC
CTRLE
183