M55800A Atmel Corporation, M55800A Datasheet - Page 28
M55800A
Manufacturer Part Number
M55800A
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.M40800.pdf
(153 pages)
3.M55800A.pdf
(29 pages)
4.M55800A.pdf
(256 pages)
5.M55800A.pdf
(28 pages)
Specifications of M55800A
Flash (kbytes)
0 Kbytes
Pin Count
176
Max. Operating Frequency
33 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
58
Ext Interrupts
58
Usb Speed
No
Usb Interface
No
Spi
1
Uart
3
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
72
Resistive Touch Screen
No
Dac Channels
1
Dac Resolution (bits)
10
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
8
Self Program Memory
NO
External Bus Interface
1
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.3/5.0
Fpu
No
Mpu / Mmu
no / no
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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Write Data Hold Time
28
AT91X40 Series
Figure 15. Early Read Protocol
Figure 16. Early Read Wait State
During write cycles in both protocols, output data becomes valid after the falling edge of
the NWE signal and remains valid after the rising edge of NWE, as illustrated in Figure
17. The external NWE waveform (on the NWE pin) is used to control the output data tim-
ing to guarantee this operation.
It is therefore necessary to avoid excessive loading of the NWE pins, which could delay
the write signal too long and cause a contention with a subsequent read cycle in stan-
dard protocol.
ADDR
MCKI
NWE
NRD
NCS
or
ADDR
MCKI
NWE
NCS
NRD
Write Cycle
Early Read Wait
Read Cycle
1354D–ATARM–08/02
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