M55800A Atmel Corporation, M55800A Datasheet - Page 32

• Manufacturer Part Number: M55800A
• Manufacturer: Atmel Corporation

Specifications of M55800A

• Flash (kbytes): 0 Kbytes
• Pin Count: 176
• Max. Operating Frequency: 33 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 58
• Ext Interrupts: 58
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Uart: 3
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 72
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3/5.0
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Chip Select Change Wait
States
32
AT91X40 Series
Additional constraints are applicable to the AT91R40807, the AT91M40807 and the
AT91 40800. The behavior of the EBI is correct when NWAIT is asserted during an
external memory access:
•
•
These constraints are not applicable to the AT91R40008.
A chip select wait state is automatically inserted when consecutive accesses are made
to two different external memories (if no wait states have already been inserted). If any
wait states have already been inserted, (e.g., data float wait) then none are added.
Figure 21. Chip Select Wait
Notes:
When NWAIT is asserted before the first rising edge of MCKI
When NWAIT is de-asserted and at least one standard wait state remains to be
executed
1. Early Read Protocol
2. Standard Read Protocol
NCS1
NCS2
NWE
NRD
MCK
(1)
Mem 1
(2)
Chip Select Wait
Mem 2
1354D–ATARM–08/02