M55800A Atmel Corporation, M55800A Datasheet - Page 89

• Manufacturer Part Number: M55800A
• Manufacturer: Atmel Corporation

Specifications of M55800A

• Flash (kbytes): 0 Kbytes
• Pin Count: 176
• Max. Operating Frequency: 33 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 58
• Ext Interrupts: 58
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Uart: 3
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 72
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3/5.0
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

WD: Watchdog Timer
1354D–ATARM–08/02
MCKI/1024
MCKI/128
MCKI/32
MCKI/8
WD_RESET
Advanced
Bus (APB)
Peripheral
WDIRQ
The AT91X40 Series has an internal watchdog timer which can be used to prevent sys-
tem lock-up if the software becomes trapped in a deadlock. In normal operation the user
reloads the watchdog at regular intervals before the timer overflow occurs. If an overflow
does occur, the watchdog timer generates one or a combination of the following signals,
depending on the parameters in WD_OMR (Overflow Mode Register):
•
•
•
The watchdog timer has a 16-bit down counter. Bits 12-15 of the value loaded when the
watchdog is restarted are programmable using the HPVC parameter in WD_CMR
(Clock Mode). Four clock sources are available to the watchdog counter: MCK/8,
MCK/32, MCK/128 or MCK/1024. The selection is made using the WDCLKS parameter
in WD_CMR. This provides a programmable time-out period of 1 ms to 2 sec. with a 33
MHz system clock.
All write accesses are protected by control access keys to help prevent corruption of the
watchdog should an error condition occur. To update the contents of the mode and con-
trol registers it is necessary to write the correct bit pattern to the control access key bits
at the same time as the control bits are written (the same write access).
Figure 35. Watchdog Timer Block Diagram
If RSTEN is set, an internal reset is generated (WD_RESET as shown in Figure 35).
If IRQEN is set, a pulse is generated on the signal WDIRQ which is connected to the
Advanced Interrupt Controller
If EXTEN is set, a low level is driven on the NWDOVF signal for a duration of 8 MCK
cycles.
Clock Select
Control Logic
CLK_CNT
Clear
Overflow
Programmable
Down Counter
16-bit
AT91X40 Series
NWDOVF
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