M55800A Atmel Corporation, M55800A Datasheet - Page 60

• Manufacturer Part Number: M55800A
• Manufacturer: Atmel Corporation

Specifications of M55800A

• Flash (kbytes): 0 Kbytes
• Pin Count: 176
• Max. Operating Frequency: 33 MHz
• Cpu: ARM7TDMI
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 58
• Ext Interrupts: 58
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Uart: 3
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 72
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 8
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.3/5.0
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Protect Mode
60
Action
Calculate active interrupt (higher than current or spurious)
Determine and return the vector of the active interrupt
Memorize interrupt
Push on internal stack the current priority level
Acknowledge the interrupt
No effect
(2)
AT91X40 Series
(1)
The Protect Mode permits reading of the Interrupt Vector Register without performing
the associated automatic operations. This is necessary when working with a debug
system.
When a Debug Monitor or an ICE reads the AIC User Interface, the IVR could be read.
This would have the following consequences in Normal Mode.
•
•
In either case, an End of Interrupt command would be necessary to acknowledge and to
restore the context of the AIC. This operation is generally not performed by the debug
system. Hence the debug system would become strongly intrusive, and could cause the
application to enter an undesired state.
This is avoided by using Protect Mode.
The Protect Mode is enabled by setting the AIC bit in the SF Protect Mode Register (see
“SF: Special Function Registers” on page 94).
When Protect Mode is enabled, the AIC performs interrupt stacking only when a write
access is performed on the AIC_IVR. Therefore, the Interrupt Service Routines must
write (arbitrary data) to the AIC_IVR just after reading it.
The new context of the AIC, including the value of the Interrupt Status Register
(AIC_ISR), is updated with the current interrupt only when IVR is written.
An AIC_IVR read on its own (e.g. by a debugger), modifies neither the AIC context nor
the AIC_ISR.
Extra AIC_IVR reads performed in between the read and the write can cause unpredict-
able results. Therefore, it is strongly recommended not to set a breakpoint between
these two actions, nor to stop the software.
The debug system must not write to the AIC_IVR as this would cause undesirable
effects.
The following table shows the main steps of an interrupt and the order in which they are
performed according to the mode:
Notes:
If an enabled interrupt with a higher priority than the current one is pending, it would
be stacked
If there is no enabled pending interrupt, the spurious vector would be returned.
1. NIRQ de-assertion and automatic interrupt clearing if the source is programmed as
2. Software that has been written and debugged using Protect Mode will run correctly in
level sensitive.
Normal Mode without modification. However, in Normal Mode the AIC_IVR write has
no effect and can be removed to optimize the code.
Read AIC_IVR
Read AIC_IVR
Read AIC_IVR
Read AIC_IVR
Read AIC_IVR
Write AIC_IVR
Normal Mode
Read AIC_IVR
Read AIC_IVR
Read AIC_IVR
Write AIC_IVR
Write AIC_IVR
Protect Mode
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